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Questions tagged [yosys]

Yosys is an open-source framework for (Verilog) HDL synthesis and formal verification. It is highly customizable using scripts and a C++ extensions API.

Yosys is an open-source framework for (Verilog) HDL synthesis and formal verification. It is highly customizable using scripts and a C++ extensions API.

180 questions
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Yosys synthesys - is this opimum?

I'm using yosys to synthesize simple circuits and show how the result varies with the cell library. However, it looks like the result is not well optimized. I'm using the library vsclib013.lib downloaded from:…
etnapoli
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How to get numbered internal wire name dump_module Yosys

I'm trying to debug how the printing in write_verilog works. What is most curious to me that I'm unable to replicate the wire name for Yosys created intermediate wires. If I take for example void dump_sigchunk(std::ostream &f, const RTLIL::SigChunk…
ChaoJJ
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Parse Error on Vivado while simulation an EDIF file

I have generated an EDIF file using Yosys, and I'd like to do post-synthesis simulation on Vivado. However, I get the following parse error. Do you have any idea, what would cause this error? I'm using Yosys 0.9+3981 and Vivado 2018.3 Parse…
shagha
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Only XOR gate synthesizing Yosys

I want to synthesize a circuit with Yosys, but I want the synthesized circuit to consist only of XOR gates. how should I do?
demirmehmet0
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How can I Invoke interactive shell with initial input as SCons Phony target?

While implementing custom SCons toolchain, I've encounter situation when I need to invoke shell as Phony target with initial input already provided, so I can continue to provide input to already invoked command. Basically, what I want is to declare…
Valery Kameko
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Executing additional command in Backend that takes the to be generated file

I'm currently looking for a way to execute iverilog in in Yosys, to be more exact at the write_verilog step. I need to feed iverilog the file, which will be generated by write_verilog (reason is, I need to uphold the variable source information,…
ChaoJJ
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Is there an option to synthsise some code into verilog built-in primitives?

I thought that techmap without any argument will do it but it didn't. probably I missunderstand what 'logical synthsis' means. basic example: AND_GATE.v: module AND_GATE( input A, input B, output X); assign X = A & B; endmodule yosys>…
Idan Zaguri
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ghdl-yosys-plugin compilation failed

I am about to test GHDL and Yosys as a replacement of EDA proprietary design flows, for my students. My point is about VHDL synthesis. I have a fresh install of several tools : trellis (ECP5), yosys, nexpnr, fujprog (ulx3s). GHDL is also installed…
JCLL
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Strange behaviour of yosys on FSM while building for iCE40

I have been toying with SpinalHDL and its SoCs and modules, but came to a general problem - almost none of the code that uses FSMs works. I nailed this issue down to Yosys, which does something weird when it detects a FSM. Here below is a simple and…
pointcheck
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ABC synthesis - read_liberty

I'm using abc01008.exe to synthesize combinational functions. I have been using mcnc.genlib and stdcell.lib with no problems. I would like to use a different std_cell libray that is in the liberty format. When I type 'rty' or 'read_liberty' I do get…
etnapoli
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Path options for techmap calls in a pass

I'm extending Yosys with a pass I made myself. In this pass, I call the techmap pass multiple times, with a path to the map to apply. However, depending on the directory I'm in while calling my pass, the correct paths to the maps differ. Is there a…
kiba42
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Using macros for defining bus fields

I am trying to use macros to define different bus bitfields in the following way: // bitfields NC / YC / XC // 0:2 / 3:(WIDTH+2) / (WIDTH+2+1): WIDTH+(WIDTH+2) // first `ifdef VStrLite `define WIDTH = 10; `else `define…
sergicuen
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Adding cell to write_verilog causes error

first of all, I'd like to say I'm not well versed in c++ or verilog at all, so I have a few problems implementing things in Yosys. I'm currently looking for a way to implement a naive information flow tracking approach to write_verilog. The way I…
ChaoJJ
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How to pass Induction in SymbiYosys?

I am very new to formal verification and I started my formal verification with SymbiYosys. I had written some code in System Verilog for learning formal verification, I was able to pass BMC and cover for the code but it is failing (UNKNOWN sate) for…
Shashidhar B
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In Yosys I am getting a Warning saying Literal has a width of 8 bit, can anyone elaborate on it

In Yosys I am getting a Warning saying Literal has a width of 8 bit, can anyone elaborate on it since i am new to yosys and I could not find any resource to understand the reason for the warning. below is the warnings from yosys: Warning: Literal…
Shashidhar B
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