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I would like to write verilog that can be synthesized either using yosys (preferable) or the Lattice Radiant tool chain using Synplify (needed for encrypted IP from Lattice for example).
Most of the hard cells like the PLL have different names between the two tools.
Is there a verilog library that allows one to choose either synthesis tool with a single 'define for example?

Moon
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Venkat
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Unfortunately not, the open source iCE40 flow was developed before Radiant existed; so used the original iCEcube primitive library (which is still the only option for devices pre-UltraPlus). For reference this is documented at http://www.latticesemi.com/~/media/LatticeSemi/Documents/TechnicalBriefs/SBTICETechnologyLibrary201608.pdf - imo it is Lattice who are at fault for failing to provide backwards compatibility with their own library...

gatecat
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    Thanks for the info David, I agree, it seems strange that lattice didnt make their newer library backward compatible! Given this fact though, would it make sense to create a small wrapper library that can allow users to switch easily between the 2 toolchains without changing code? – Venkat Oct 25 '19 at 19:10
  • Yes, unfortunately it's harder than it looks because the original library correctly uses proper Verilog numeric parameters (e.g. constants like 16'h5a5a) whereas the Radiant one uses C-style literals inside Verilog string parameters (so you have to parse something like "0x5a5a") – gatecat Oct 25 '19 at 19:55