Trying to implement a stack in Verilog. What's wrong with the code?

Question

I'm new to Verilog, so please excuse any newbie mistakes. I'm trying to implement a 3 byte stack in verilog. Using R_W to read write (push/pop) and a 2D Array to store the contents of the stack.

`timescale 1ns / 1ps

 module one(R_W,PUSH,POP);

 input PUSH;
 input  R_W;
 output POP;

 wire [31:0] PUSH;
 reg [31:0] POP;
 wire R_W;

 reg [31:0] temp[0:3];
 integer tos = 3;

 if(R_W == 1 && tos != 3)
   begin
     POP = temp[tos];
   end

 if(R_W == 0 && tos != 0)
  begin
    tos = tos +1;
    POP = temp[tos]; 
  end


endmodule

Test Bench

`include"one.v"
module one_test();

wire pop;
reg [31:0] push;
wire r_w;

initial begin

push = 2'd12;
r_w = 0;

#10

$finish;

end


one one(r_w,push,pop);

endmodule

What is your question? Please check out [the Stack Overflow help](http://stackoverflow.com/help). — Matthew Taylor, Jun 20 '16 at 07:44
You are missing an `always` block. You probably need a clock and/or enable signal as well. — Greg, Jun 20 '16 at 17:39

score 1 · Answer 1 · answered Jun 23 '16 at 07:10

Thanks for the code correction Renato, but I've improved the code and used the PUSH functionality too. Given below is the code along with the Test Bench in Verilog:

MODULE:

`timescale 1ns / 1ps

module some(clk,R_W,PUSH,POP);

input clk;
input [31:0] PUSH;
input  R_W;
output [31:0] POP;

wire [31:0] PUSH;
reg [31:0] POP;
wire R_W;

reg [31:0] temp[0:3];
integer tos = 3;

always @ (posedge clk)
if(R_W == 1 && tos != 3)
  begin
    POP = temp[tos];
    tos = tos + 1;
  end
else if(R_W == 0 && tos != 0)
  begin
    temp[tos] = PUSH; 
    tos = tos - 1;
  end

endmodule

TEST BENCH

module some_test();

reg clk;
reg r_w;
integer push;
wire [31:0] pop;

always begin

#1 clk = !clk;

end

initial begin

clk = 0;

#1 r_w = 0;

#1 push = 'd9;

#10
$finish;

end

some some(clk,r_w,push,pop);

endmodule

What could happen when the stack is empty and want to read its content? What could happen on stack overflow and underflow errors? Should't have it an `error` line, for example? — Piranna, Feb 27 '17 at 05:52

score 0 · Answer 2 · answered Jun 20 '16 at 08:47

0

Two things:

You're implementing a 3-word stack, not a 3-byte stack.

I am not sure what tos is but suppose it is how many items left in the stack then you have two things wrong. Here is the correct code

`timescale 1ns / 1ps

module one(R_W,PUSH,POP);

input PUSH;
input  R_W;
output POP;

wire [31:0] PUSH;
reg [31:0] POP;
wire R_W;

reg [31:0] temp[0:3];
integer tos = 3;

if(R_W == 1 && tos != 3)
  begin
    tos = tos + 1;
    POP = temp[tos];
  end

if(R_W == 0 && tos != 0)
  begin
    tos = tos - 1;
    POP = temp[tos]; 
  end

endmodule

I am not sure about syntax since I'm more of a VHDL guy myself. But since there was something wrong with the tos logic. I decided to answer it.

answered Jun 20 '16 at 08:47

Renato

178
1
13

Yes. Sorry. I meant 3 word stack. And tos stands for top of stack. And the problem's mainly with the syntax. I'm new to these data types and how Verilog works. Sorry for the needy post and thank you for your answer. – gambhirprateek Jun 20 '16 at 08:56
So if it is syntax what is the error message the compiler gives you? You still have a problem with **tos** in your original code. – Renato Jun 20 '16 at 08:59
Line 18: Syntax error near "=".------------------------- Line 24: Syntax error near "=".-------------------------- Line 16: R_W is not a constant-------------------------- Line 18: tos is an unknown type-------------------------- Line 19: POP is an unknown typeLine 22: R_W is not a constant-- Line 24: tos is an unknown type---------------------------- Line 25: POP is an unknown type------------------------- Line 3: Module ignored due to previous errors---------------. Verilog file ignored due to errors--------------------- – gambhirprateek Jun 20 '16 at 09:07
Also Verilog doesn't allow selection of slices from arrays as I've done in the above code that's a feature available only in systemVerilog. I just wish there were guided systematic tutorials on Verilog. I'm looking for projects to do on a virtex 5 – gambhirprateek Jun 20 '16 at 09:12

score 0 · Answer 3 · answered Jun 21 '16 at 07:47

Ok! Here is the corrected code. It should compile now:

`timescale 1ns / 1ps

module one(clk,R_W,PUSH,POP);

input clk;
input [31:0] PUSH;
input  R_W;
output [31:0] POP;

//wire [31:0] PUSH;
reg [31:0] POP;
wire R_W;

reg [31:0] temp[0:3];
integer tos = 3;

always @ (posedge clk)
if(R_W == 1 && tos != 3)
  begin
    POP = temp[tos];
    tos = tos + 1;
  end
else if(R_W == 0 && tos != 0)
  begin
    POP = temp[tos]; 
    tos = tos - 1;
  end

endmodule

There is one major difference. I was not sure if you need your design synchronous to a clock. Normally in a stack operation you need this. But if you want to make it a combinatorial exercise without a clock here is the code for that:

`timescale 1ns / 1ps

module one(R_W,PUSH,POP);

input [31:0] PUSH;
input  R_W;
output [31:0] POP;

//wire [31:0] PUSH;
reg [31:0] POP;
wire R_W;

reg [31:0] temp[0:3];
integer tos = 3;

always @ (R_W, tos)
if(R_W == 1 && tos != 3)
  begin
    POP = temp[tos];
    tos = tos + 1;
  end
else if(R_W == 0 && tos != 0)
  begin
    POP = temp[tos]; 
    tos = tos - 1;
  end

endmodule

Trying to implement a stack in Verilog. What's wrong with the code?

3 Answers3