Error while checking syntax

Question

module mult(a, b, p);     
input [16:0] a;     
input [16:0] b;     
output p;    
wire [31:0] p;   
reg i;       
wire pv;     
wire bp; 
assign pv = 32'b0; 
assign bp = {16'b0,b} ; 
initial begin 
for (i = 0; i < 32 ; i = i + 1)     
    begin       
    if (a[i] == 1'b1)           
    begin               
       pv <= pv + bp;           
    end                 
    bp <= bp << 1 ;     
    end 
end 
assign p = pv;   
endmodule

I get the following error while compiling the code, line 37 Reference to scalar wire 'pv' is not a legal reg or variable lvalue line 37 Illegal left hand side of nonblocking assignment line 39 Reference to scalar wire 'bp' is not a legal reg or variable lvalue line 39 Illegal left hand side of nonblocking assignment

Pls help.

This code demonstrates lack of understanding fundamental Verilog concepts. Before trying to fix your code, learn the differences and usages of `wire` vs `reg` vs `integer` as well as `assign` vs `initial` vs `always`, and blocking assignments (`=`) vs non-blocking assignments (`<=`) — Greg, Feb 14 '17 at 19:50

Laleh · Answer 1 · 2017-02-14T21:06:24.270

0

Left hand side of assignment in always and initial blocks must be registers. pv and bp are wires instead of registers.

you cannot put a variable in left hand side of assign and always block at the same time. Because always needs registers and assign needs wires.

I see obvious semantic mistakes in your code . You need to study basics of Verilog. You put assign which means you expect a continuous assignment but an initial block is executed just once in the beginning of simulation. By the way output is wire by default. you can declare it as output [31:0] p;

edited Feb 14 '17 at 21:06

answered Feb 14 '17 at 06:49

Laleh

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3
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if i assign registers to pv and bp. I get the following error vERROR:HDLCompilers:246 - "mult.v" line 30 Reference to scalar reg 'pv' is not a legal net lvalue ERROR:HDLCompilers:53 - "mult.v" line 30 Illegal left hand side of continuous assign Hence i had put it as reg, what should i do? – prakash Sri Feb 14 '17 at 08:29
ERROR:HDLCompilers:247 - "mult.v" line 31 Reference to scalar wire 'pv' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "mult.v" line 31 Illegal left hand side of blocking assignment ERROR:HDLCompilers:247 - "mult.v" line 36 Reference to scalar wire 'pv' is not a legal reg or variable lvalue ERROR:HDLCompilers:106 - "mult.v" line 36 Illegal left hand side of nonblocking assignment ERROR:HDLCompilers:247 - "mult.v" line 38 Reference to scalar wire 'bp' is not a legal reg or variable lvalue ERROR:HDLCompilers:106 - "mult.v" line 38 Illegal left hand side of nonblocking assign – prakash Sri Feb 14 '17 at 14:09
@Laleh , there are 3 major issues with your answer. **(1)** code will only execute at time 0 (how to do synthesizable continuous procedural blocks?). **(2)** infinite for-loop (can you figure out why?). **(3)** incorrect result (how does non-blocking work?) – Greg Feb 14 '17 at 20:03
I know! As I mentioned this code has many semantic errors. I just change it to be compiled! – Laleh Feb 14 '17 at 20:17

Error while checking syntax

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