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I'm working on a school homework and I'm finding difficulties in outputing an array with values of 1.I used this code,but the simulator keeps filling the signal bar with X

    integer index = 0;
initial
begin
for(index=0;index<=7;index = index+1)
    begin
     data_out[index]<=1;
    end
end
endmodule

data_out is declared as output reg [7:0]data_out

Can anyone suggest me anything?

Dragos Alexe
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  • i have connected the data_out output this way reg [7:0] data_out_test and initialized it .data_out(data_out_test); – Dragos Alexe May 14 '16 at 21:37
  • You need to show more code for help tracking this down. There are too many places it could go wrong. Create a [MCVE](http://stackoverflow.com/help/mcve) and edit your question to include that instead. If you provide a complete example that I can copy into a text editor and run, I can test it out. – skrrgwasme May 14 '16 at 21:40
  • I'm suggesting you create a MCVE for two reasons: 1) You'll often figure out errors yourself while doing so, and 2) the error could be a mismatch between the declarations and the assignments you're showing, how the modules are connected, or how you're printing. Since you're only showing one of the three, there's no way for us to help you track it down. – skrrgwasme May 14 '16 at 21:51
  • I will post a MCVE tomorrow even though it will be kind of difficult for me to try to explain the whole program. I hoped it was a declaration mistake and it could be solved easy . – Dragos Alexe May 14 '16 at 22:04
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    Why are you using an `initial` instead of an `always` block? Is this for a testbench? – wilcroft May 15 '16 at 02:49
  • If data_out is an output of this module, then you must have: `wire data_out_test; .data_out(data_out_test); `. Note the usage of `wire`. Also, you might intend to use always block. – rahulcodesinverilog May 15 '16 at 07:39
  • Ok,I modified to an `always` block and tried with both `wire data_out_test;` and `reg[7:0] data_out_test` . I did not used `wire` before because I wanted the output to be shown in 8 bit . It's still not working :( – Dragos Alexe May 15 '16 at 09:18
  • Ok,and next . I have a descending order counter and another variable . `integer index = 0; always@(posedge clock) begin for(index=0;index<=31;index = index+1) begin if(count > suma_de_1) data_out[index]<=2'b00; else data_out[index]<=1; end end` It's [31:0] not [7:0] anymore . But at the time the counter is bigger than suma_de_1 it still shows me on the simulator the value of 1 . Any suggestion? – Dragos Alexe May 15 '16 at 09:45
  • @wilcroft any ideea ? – Dragos Alexe May 15 '16 at 13:16

1 Answers1

0

It works now , as i've used wire[7:0] data_out_test and always block. Thank you for your answers

Ok,and next . I have a descending order counter by the posedge clock and another variable suma_de_1 whose value is 12.The counters stars from 31 to 0 and i have the following if condition 

`integer index = 0;
always@(posedge clock) begin
for(index=0;index<=31;index = index+1) 
begin 
if(count > suma_de_1) 
data_out[index]<=2'b00; 
else data_out[index]<=1; 
end end`

check this out to see the result waveform

at that point count becomes smaller than suma_de_1 but it creates another array . I want it to complete the previous array who was full of 0 until then. Hope I'm clear enough. I want the output in one array,not two

Dragos Alexe
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