Highest Voted 'xilinx-ise' Questions

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Converting std_logic to integer within testbench?

I'm trying to return a value of a CLK signal at a specific time in the Console Window of ISim (shown in my code below, 7.5ns). I'm getting this error: ERROR:HDLCompiler:258 - "saved project.." Line 91: Cannot convert type std_logic to type…

vhdl xilinx xilinx-ise

asked Jul 29 '15 at 14:17

VKkaps

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3 answers

Xilinx / ISim seem claims value to be X but it has been declared

Have JUST started learning how to use this tool so if my question seems silly i apologize in advance. I have searched the error in numerous forums (already answered posts , not mine) and couldn't understand what i was doing wrong so here is my…

vhdl xilinx xilinx-ise

asked Jul 11 '15 at 00:25

stonedevil

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Where's the latch in my VHDL program?

I have a latch involving my signal d_reg in this code. I'm new to VHDL and I can't seem to find the reason for this latch. I've already assigned d_reg a value for every case of in_data. Could anyone explain why I have a latch, and how to prevent…

vhdl fpga xilinx-ise

asked Jul 07 '15 at 15:07

Eugene Wu

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2 answers

Arithmetic operation of Fixed point with Std_logic_vector in VHDL

I am writing a code in VHDL for arithmetic operations with the signals. I declared signals as follows: signal x : std_logic_vector (7 downto 0); signal y: std_logic_vector (7 downto 0); signal z: std_logic_vector ( 7 downto 0); …

floating-point hex vhdl fixed-point xilinx-ise

asked May 26 '15 at 08:01

user4866219

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2 answers

Verilog code works very well in Simulation but not on FPGA

I having been trying to implement a simple sequence detector on a Nexys 3 (Spartan 6) board. The code works perfectly on Xilinx simulation but on the hardware, it doesn't work. Since I am new to FPGA implementation I couldn't solve this issue. I…

verilog simulation fpga xilinx-ise

asked Mar 26 '15 at 17:05

Jithin Sreenivasan

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Advanced verilog design analysis

I'm trying to implement a design into a Virtex II Pro FPGA (from Xilinx). The problem is the design is overmapped, taking up too many resources. To overcome that, I needed to know which blocks of my code are the most demanding (require more…

optimization verilog fpga xilinx xilinx-ise

asked Mar 12 '15 at 00:05

Luis Filipe Martins Barros

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1 answer

start point for partial reconfiguration in xilinx virtex 5 board

I,m going to learn working with partial reconfiguration xilinx boards. I've read xilinx guide and know about ISE, plan ahead and vivado. but for starting I couldn't find any example. Is there simple example codes for beginning? steps of making…

xilinx-ise vivado

asked Mar 05 '15 at 09:59

nasir khani

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Verilog Synthesis Takes Too Long

I am writing a synthesizable module in Verilog in the Xilinx ISE. Part of it is creating a 256x128x1 array with 1 bit in each of its cells and filling this array 1 bit at a time on every rising clock edge. I've decided to ignore any for and while…

verilog digital xilinx-ise

asked Feb 21 '15 at 18:57

thatguyoverthere

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ERROR:Simulator:702 - Can not find design unit work.glbl ... when attempting Post-Route in ISim

I am trying to run my project in Post-Route simulation. The behavioral simulation works fine and I want it to work on the Spartan 3E Starter board. It also is able to Generate a Programming File under implementation. Using ISE 14.7 The error I get…

verilog simulation xilinx-ise

asked Dec 06 '14 at 21:12

exrhizo

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3 answers

Distributable fpga design

I'm new to fpga programming, and I'm wondering how to make my fpga design distributable. Here's the scenario I have in mind. I have a network of computers, each deployed with an fpga based peripheral. I want to update the fpga design on the…

fpga software-distribution xilinx-ise

asked Nov 27 '14 at 00:26

user3284794

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1 answer

What's wrong with this signal assignment?

When I compile with Xilinx 9.1i, It tells me: "Line 91. Type of Tens is incompatible with type of tensOut." "Line 92. Type of Ones is incompatible with type of onesOut." But both are std_logic_vector (7 downto 0) Here's the code: library IEEE; use…

vhdl xilinx xilinx-ise

asked Oct 23 '14 at 14:53

Jay Sonsona

50
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1 answer

FPGA spartan 3 - X mod 3 inside combinatorial process without clock

I am working on a project which one part pivots around finding X mod 3 with and FPGA spartan 3 (Xilinx), inside a combinatorial process. in fact in this project there are some other modules which are sequential, before this ALU module. but inside…

vhdl fpga modelsim xilinx-ise

asked Oct 05 '14 at 23:00

manpmanp

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1 answer

ChipScope Error - Did not find trigger mark in buffer

Has anybody mentioned data errors, trigger error or upload errors in ChipScope? I'm using ChipScope (from ISE 14.7) with the IP core flow. So I created 15 different ICON IP cores as ngc files and wrapped them all in a VHDL module. This module…

fpga xilinx virtex xilinx-ise

asked Sep 12 '14 at 08:12

Paebbels

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launching ise14.6 on ubuntu 12.4

I have installed "ise14.6" on "ubuntu".but after installation, I do not know how to launch it. I have read somewhere that I must source setting.sh .but there is no such file in folder i have installed "ise14.6" .would you please help. I need for…

ubuntu ubuntu-12.04 launch xilinx-ise

asked Jun 04 '14 at 17:22

fatemeh

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Installation Cannot be performed fix this issue before installing. Virtualization is not enabled in BIOS Please enable before installing?

I had already enabled Virualization from "BIOS". But still I am unable to install please help?? Is there is any alternate other then Xilinx.

xilinx xilinx-ise xilinx-edk

asked Oct 01 '22 at 11:44

vishal singh

9
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Questions tagged [xilinx-ise]