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Questions tagged [xilinx-ise]

Xilinx ISE is the toolchain package for programming Xilinx FPGAs in VHDL and Verilog.

291 questions
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Machine state does not change output

As you can see in the code below, I have a machine state with a state called start. This state should take the value of coord_x_reg , increment it by one and assign it to the output port using the assign instruction at the end. The problems…
Ginés Díaz
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Dump all values of input outputs of submodule in vhdl project

I have build a cpu in vhdl. The cpu contains alu, ram, mux and other submodules. Now I want to dump all the values of inputs and outputs of submodules into csv or vcd files. I want to observe the changes for suppose 20 clock cycle. How can I do it…
Maruf Monem
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How to Write data from FPGA to DDR3 memory without PS Logic

I'm using zynq7000 family fpga, i want to write data from my fpga to micron ddr3 sdram memory without using PS logic (only using PL) I'm new to memory based designs may i get any help to design the logic using PL or any references. Thanks in…
manu
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Controlling ADC data rates using FPGA

I need to control sampling frequency of ADCs interfaced with my FPGA. I can use a 50MSPS, 14 bit resolution ADC. and then using DCM divide the FPGA source 50MHz clock to 1MHz, 2MHz and 5MHz and use these frequencies each time as the clock of my…
Fateme
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No Signal Shown in Isim simulation

i am working on a vhdl code which is supposed to do many functionalities.my code and also my test bench are working fine. but in simulation nothing is initialized. and i dont really understand why and where exactly is my mistake.i would appreciate…
maryam ghanbari
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Simple code yielding error even though syntax seems correct (ISE VERILOG)

I am relatively very new(just a few hours old) in Xilinx ISE verilog coding. This is my code from my uni project. And it shows syntax error on the count = 0 line. I dont see anything wrong here upon running check syntax. How do i fix this? module…
Bossman Flag
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16bit multiplier vhdl code synthesize error

I want to write a 16bit * 16bit multiplication code. Here is my code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity mul is port ( A, B: IN INTEGER RANGE -32768 TO 32767; C: OUT INTEGER RANGE -2147483648 TO +2147483647 …
Benyamin
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Integer output turns to binary in synthesize ISE

I have a VHDL BCD counter whose output is an integer value (digit). But when I simulate the code in Xilinx ISE it shows the code's waveform in binary value. The code works but the output should be integer but it's not. I have tested this code in…
Benyamin
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my vhdl code for implementing some fsm is not working correctly

library IEEE; use IEEE.std_logic_1164.all; entity INCUBATOR2 is port(temperature: in std_logic_vector(7 downto 0); CLK,RESET: in std_logic; on_cooler,on_heater: out std_logic; CRS:out std_logic_vector(3 downto 0)); end entity…
fatecsa
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VHDL entity definition

I am using a few resources on the internet to learn processor and motherboard design and I came across the error: VHDL: Syntax error near end. I am fairly new to this and can't seem to pin-point the fault. Any help would be greatly…
DarkestSoul1992
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VHDL-unconnected warning, 4 digit codelock

I am working on a project and I'm failing to to figure it out. I just can't see what I'm doing wrong. Any suggestions are highly appreciated. This project is in VHDL and this is about 4 digit combination lock in Spartan 3e starter board. It's my…
smit
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Frequency Divider and subsequent edge detection of the signal

I'm very new to the world of VHDL programming and I am having issues implementing a frequency divider along with the detection of the edges of a signal. The code consists of 6 button inputs in which each one will operate and outputting pulse at 1KHz…
Mak Buck
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VHDL parse error, unexpected INTEGER_LITERAL, expecting RETURN or IDENTIFIER or RSQBRACK Process "Check Syntax" failed

I am writing a VHDL Program for 4:1 MUX and am facing a error on the line where process clause starts library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity mux_41 is Port ( inp : in STD_LOGIC_VECTOR (0 downto 3); outp : out …
KshitijV97
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VHDL Simple Seven Segment Display on Basys2 FPGA board

So I am new to the FPGA world, and I am new to the VHDL language. I tried to light up my seven segment displays, but I always come across with an error. The below code just works on displaying number one on the seven segement when the switch is on…
Fuzzyy
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Wait for input state change to start process

I'm programming a Coolrunner2 (XC2C64A) CPLD with the ISE Project Navigator software. For now, it should only act as a logical or gate (output = o_buzzer) between a pin from a PIC32 (input = i_pic) and a RPi CM3 (input = i_cm). o_buzzer <= i_pic or…
Swedgin
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