Converting std_logic to integer within testbench?

Question

I'm trying to return a value of a CLK signal at a specific time in the Console Window of ISim (shown in my code below, 7.5ns). I'm getting this error:

ERROR:HDLCompiler:258 - "saved project.." Line 91: Cannot convert type std_logic to type unsigned

I've used this conversion ( integer'image(to_integer(unsigned((generic_signal)))); ) with std_logic_vectors and it worked fine, but this one won't take. The CLK value is a 0 or a 1, I just want to return that value at a given time. Do you know of a more efficient way of doing this? Do you happen to know of a link where I can see more ways to return variable values using 'image

   library IEEE;
    use IEEE.STD_LOGIC_1164.all;
    use IEEE.NUMERIC_STD.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;

-----------------------------------------------------------
-- Component Declaration for the Unit Under Test
-----------------------------------------------------------
component SyncPosEdge port(
   SYS_CLK : in std_logic;
   InputSignal : in std_logic;
   SyncOutputSignal : out std_logic);
end component;

-----------------------------------------------------------
-- Inputs
-----------------------------------------------------------
signal SYS_CLK : std_logic := '0';
signal InputSignal : std_logic := '0';

-----------------------------------------------------------
-- Outputs
-----------------------------------------------------------
signal SyncOutputSignal : std_logic;

-----------------------------------------------------------
-- Clock period definitions
-----------------------------------------------------------
constant SYS_CLK_period : time := 5 ns;
constant InputPeriod : time := 15 ns;

begin

-----------------------------------------------------------
-- Instantiate the Unit Under Test
-----------------------------------------------------------
uut:SyncPosEdge port map(
   SYS_CLK => SYS_CLK,
   InputSignal => InputSignal,
   SyncOutputSignal => SyncOutputSignal);

-----------------------------------------------------------
-- Clock process definitions
-----------------------------------------------------------
SYS_CLK_process:process
begin
   SYS_CLK <= '0';
   wait for SYS_CLK_period / 2;
   SYS_CLK <= '1';
   wait for SYS_CLK_period / 2;
end process SYS_CLK_process;

-----------------------------------------------------------
-- Generate Input Signal
-----------------------------------------------------------
InputGen:process
begin
   InputSignal <= '0';
    wait for InputPeriod / 2;
    InputSignal <= '1';
    wait for InputPeriod / 2;
end process;

-----------------------------------------------------------
-- Stimulus process
-----------------------------------------------------------
stim_proc:process
begin   
   wait for 7.5 ns;
    report "SYS_CLK: " & integer'image(to_integer(unsigned((SYS_CLK))));

   wait;
end process stim_proc;

score 1 · Accepted Answer · answered Jul 29 '15 at 14:25

1

You can easily print an std_logic using the image attribute:

report "SYS_CLK: " & std_logic'image(SYS_CLK);

answered Jul 29 '15 at 14:25

scary_jeff

4,314
13
27

yup, that fixes it, thanks! Do you know where I can find a complete list of _'image options_ and conversions in Xilinx or online? I'd like to reference that as opposed to asking online everytime ya know? – VKkaps Jul 29 '15 at 14:32
1

Any good book on VHDL should have that information. My suggestion would be Peter Ashenden's "Designer's Guide to VHDL" – Jul 29 '15 at 14:47
1

I usually look at this page http://www.csee.umbc.edu/portal/help/VHDL/attribute.html for attributes, and I've got this image on the wall in front of me http://www.bitweenie.com/wp-content/uploads/2013/02/vhdl-type-conversions.png – scary_jeff Jul 29 '15 at 15:08

Converting std_logic to integer within testbench?

1 Answers1