Where's the latch in my VHDL program?

Question

I have a latch involving my signal d_reg in this code. I'm new to VHDL and I can't seem to find the reason for this latch. I've already assigned d_reg a value for every case of in_data. Could anyone explain why I have a latch, and how to prevent this in the future?

The warning I receive is:

WARNING:Xst:1710 - FF/Latch <d_reg_0> (without init value) has a constant value of 0 in block <delay_incrementor>. This FF/Latch will be trimmed during the optimization process.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity delay_incrementor is
    Port ( clk,reset: in STD_LOGIC;
           in_data : in  STD_LOGIC_VECTOR (7 downto 0);
           out_data : out  STD_LOGIC_VECTOR (7 downto 0);
           d : out  STD_LOGIC_VECTOR (25 downto 0));
end delay_incrementor;

architecture Behavioral of delay_incrementor is
  signal d_reg,d_next: std_logic_vector (25 downto 0);
begin
  --Register
  process(clk,reset)
  begin
    if reset='1' then
      d_reg <= (others => '0');
    elsif (clk='1' and clk'event) then
      d_reg <= d_next;
    end if;
  end process;

  --Next-State Logic
  d_next <= std_logic_vector(unsigned(d_reg) + "1001100010010110100000000") when in_data = "01010101" else
             std_logic_vector(unsigned(d_reg) + "1001100010010110100000000") when in_data = "01000100" else
             d_reg;
  out_data <= "00010111" when in_data /= "00000000" else
                (others=>'0');

  --Output Logic
  d <= d_reg;
end Behavioral;

That's not a latch. It would be a FF except that you never assign '1' to that specific bit so the tools save the FF and warn you about it. It's a warning not an error, so it's safe to ignore (unless you actually meant to assign '1' to that bit sometimes) — , Jul 07 '15 at 15:28

score 2 · Accepted Answer · answered Jul 07 '15 at 15:49

2

XST Warning 1710 is just a common warning for all memory elements (latches, flip flops, ...).

The warning notes that your FF has a constant value, so a possible d input or ce clock enable is not used or change or also trimmed :).

A latch found warning is XST Warning 737:

WARNING:Xst:737 - Found n-bit latch for signal .

answered Jul 07 '15 at 15:49

Paebbels

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Specifically, the reason the value is constant is because the 25-bit `d_reg` register is reset to all `0` (and implicitly initialized to all `0`), and can only change by adding constants that have all `0` for the least significant 8 bits. It is therefore impossible for the lower 8 bits of `d_reg` to be non-zero, and the compiler optimizes away the flops there (replacing them with direct connections to `0`/ground) to save FPGA area. – QuantumRipple Jul 07 '15 at 16:29

Where's the latch in my VHDL program?

1 Answers1