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I,m going to learn working with partial reconfiguration xilinx boards. I've read xilinx guide and know about ISE, plan ahead and vivado. but for starting I couldn't find any example. Is there simple example codes for beginning? steps of making partial reconfiguration project is written in xilinx user guide(ug720) but there isn't any verilog or vhdl code to synthesis and going forward with them! Is there simple code to start with them?

nasir khani
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You could start with different counter designs. The counter works as a clock divider to generate a 2.0, 1.0 and 0.5 Hz signal, which is displayed on a LED.

Each counter is one reconfigurable design and your top module represents the mapping of the counter output to the LED pin. So if your reconfiguration works correct, the frequency should be equal to the selected partial design.

Now you can expand your design and add DCM/MMCMs, BlockRAMs or what ever.

Paebbels
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  • Thanx for your help.As your said I wrote 2 counters. another question? how can i exchange my partitions automatically. I designed the counters by plan-ahead and now I have 3 modules, but I don't know how to control exchanging them? – nasir khani May 17 '15 at 06:06
  • You should ask each question on this website in an own question so more people see your new question. – Paebbels May 17 '15 at 07:13