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Questions tagged [xilinx-ise]

Xilinx ISE is the toolchain package for programming Xilinx FPGAs in VHDL and Verilog.

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How can I write a large VHDL module and keep it readable?

I'm trying to write the control logic module for a toy processor. It cycles through the fetch/decode/execute states, reads and writes from various bits of memory, and sets a bunch of control signals. It's somewhat large, and as far as I can tell…
FusterCluck
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does after [some delay in second] statement provide delay only in simulation or in actual synthesized model to be loaded in to fpga in VHDL?

We use after [some delay] statement for providing delay and that we can analysis in simulation. But when we will load this model in to FPGA so in actual hardware being made by VHDL code will have affect of delay or this delay is limited to…
Neil Terminator
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What are the conditions when a 2D memory instantiated in Verilog is mapped to BRAM by ISE?

Upon searching in multiple forums, I did not find a comprehensive answer. I would like to understand, when does [PARAM1:0] ram [PARAM2:0] inferred as a Block RAM by the ISE synthesizer and when it is not?
Karthik Hegde
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ISE XILINX PhysDesignRules:367 - The signal <> is incomplete. The signal does not drive any load pins in the design

I am trying to connect a keyboard with a PS/2 port and the port of the basys 2 in which display the ASCII code of the key in the 8 leds. There are these warnings: WARNING:Xst:2109 - Contents of latch never changes during circuit operation.…
SantiagoBarragan
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Xilinx Floating Point Core - Erroneous 'X' values?

I've attempted to use the Xilinx pg060 Floating Point Core. After looking through the diagrams provided, such as the timing diagram above and the demo testbench (which for the inexperienced such as myself, is quite confusing!) I created a short…
davidhood2
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nested for loops in verilog that second for loop depends upon output of first for loop

I'm developing a verilog code for cumulative histogram method , for median filter . it uses nested for loops , that the input of second for loop depends on output of first for loop . the problem lies here .the second for loop is not accepting that…
Bharath Kotari
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Verilog HDL doesn't allow assignment of the value of one integer variable to another

I am writing code for 16*4 RAM in Verilog. For each binary cell of memory, I am using an SR flip-flop. Initially, each cell is assigned 1'bx. I am using integers for loops as well as to store the value of the index of memory which is to be accessed…
user2585933
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Xilinx ISIM: Count the Number of Transitions

Is there a way that I can have ISIM count the number of high to low and vice versa transitions in a given time period during a simulation?
Terry Price
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XPE and XPAnalyzer ISE calculates voltage and current based on what models?

Maybe a noob question but, I would like to know how XPA and XPE ISE calculate power, voltages or curent. I mean, I undestand all about pre or post implemenatation stuff and what's the differnce between those tools(and the results they give) , but…
The Invisible
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Interfacing with Xilinx virtex-5 FPGA board

i have been working with spartan 3e starter kit board for long time. But now i am trying to work with virtex-5 ml505 xc5vlx110t board(ff1136). And the very first problem that I am facing is that xilinx ise 14.7 does not have package of this board(it…
Utkarsh Jain
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SystemVerilog to VHDL std_logic generic

My problem is that I have to pass a generic from a SystemVerilog module to a VHDL entity of type std_logic, that will be directly used inside that entity in signal assignments. entity foo is generic( my_generic : std_logic); port (...); end…
arandomuser
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8-bit Adder Error: The logic does not match a known FF or Latch template

As far as I can understand that the hardware required to implement the code below is not supported in Xilinx ISE Web Pack. I'm trying to implement only the functionality of the 8-bit adder using an always block. Here's the code: module…
Burak.
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How long is a line after a readline(fh, line) call?

I have written a JSON parser in VHDL. The parser core uses two nested loops: 1. loop over all lines until EOF 2. loop over every char until line of end For clearance: Its not a hardware parser. the parser used to read synthesis settings at synthesis…
Paebbels
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How to reduce Calibration time for DDR3 simulation in MIG v1.9?

I am working on Artix 7 (xc7a200t-2fbg676) device. I have generated DDR3 core using MIG v1.9. When I try to simulate the design, it takes 107 us to complete calibration. The simulation runs with a step size of 20ns/s. So it takes more than 30 mins…
KharoBangdo
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VHDL is incomplete. The signal is not driven by any source pin in the design

I'm trying to write a very simple program on a Spartan-3E development board. I want to read the slide switches and use the LED next to the slide switches to indicate which switch is in the on position. Here is my code: library IEEE; use…
hfbroady
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