Xilinx ISE: found '0' definitions of operator "+", cannot determine exact overloaded matching definition for "+"

Question

I am writing Bin to BCD code Multiplier and in the top module Xilinx ISE gives this error:

Line 30: found '0' definitions of operator "+", cannot determine exact overloaded matching definition for "+"

while I have mapped the ports to the top module

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
-- library UNISIM;
-- use UNISIM.VComponents.all;

entity EightDisplayControl is
    Port ( clk : in  STD_LOGIC;
           leftL, near_leftL : in  STD_LOGIC_VECTOR (3 downto 0);
           near_rightL, rightL : in  STD_LOGIC_VECTOR (3 downto 0);
           leftR, near_leftR : in  STD_LOGIC_VECTOR (3 downto 0);
           near_rightR, rightR : in  STD_LOGIC_VECTOR (3 downto 0);
           select_display : out  STD_LOGIC_VECTOR (7 downto 0);
           segments : out  STD_LOGIC_VECTOR (6 downto 0));
end EightDisplayControl;

architecture Behavioral of EightDisplayControl is
    signal Display      : std_logic_vector(2 downto 0);
    signal div      : std_logic_vector(16 downto 0);
    signal convert_me : std_logic_vector(3 downto 0);
begin

div<= div+1 when rising_edge(clk);
Display <= div(16 downto 14); 

process(Display, leftL, near_leftL, near_rightL, rightL, leftR, near_leftR, near_rightR, rightR)
begin
    if    Display ="111" then select_display <= "11111110"; convert_me <= leftL;
    elsif Display ="110" then select_display <= "11111101"; convert_me <= near_leftL;
    elsif Display ="101" then select_display <= "11111011"; convert_me <= near_rightL;
    elsif Display ="100" then select_display <= "11110111"; convert_me <= rightL; 
    elsif Display ="011" then select_display <= "11101111"; convert_me <= leftR; 
    elsif Display ="010" then select_display <= "11011111"; convert_me <= near_leftR; 
    elsif Display ="001" then select_display <= "10111111"; convert_me <= near_rightR; 
    else                              select_display <= "01111111"; convert_me <= rightR; 
    end if;
end process;

decoder : entity work.segment_decoder 
        port map (convert_me, segments); 

end Behavioral;

pls check the VHDL FAQ for this: https://tams.informatik.uni-hamburg.de/vhdl/doc/faq/FAQ1.html#4.11 In short, std_logic_vector + interger: can not be done. More modern coding is using IEEE.numeric_std for arithmetic on vectors — vermaete, Jul 01 '20 at 08:12
Okay, changing the IEEE.numeric_std into IEEE.std_logic_unsigned? @Tricky When i changed it, there are more errors — Banana Guy, Jul 01 '20 at 08:39
No. Please ask on here. I suggest you work through the errors and fix them — Tricky, Jul 01 '20 at 13:33
[The simpler your design description](https://i.stack.imgur.com/4lH0N.jpg) the fewer errors you have to debug (hopefully through simulation). — , Jul 02 '20 at 01:19

score 0 · Answer 1 · answered Jul 01 '20 at 15:24

As has already been stated in comments, the problem is that you have defined signal div as a std_logic_vector. The IEEE.numeric_std library does not define an addition operation for std_logic_vector.

Looking in the library we see:

--============================================================================

-- Id: A.3
function "+" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(MAX(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Adds two UNSIGNED vectors that may be of different lengths.

-- Id: A.4
function "+" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(MAX(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Adds two SIGNED vectors that may be of different lengths.

-- Id: A.5
function "+" (L: UNSIGNED; R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0).
-- Result: Adds an UNSIGNED vector, L, with a non-negative INTEGER, R.

-- Id: A.6
function "+" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0).
-- Result: Adds a non-negative INTEGER, L, with an UNSIGNED vector, R.

-- Id: A.7
function "+" (L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0).
-- Result: Adds an INTEGER, L(may be positive or negative), to a SIGNED
--         vector, R.

-- Id: A.8
function "+" (L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0).
-- Result: Adds a SIGNED vector, L, to an INTEGER, R.

--============================================================================

This clearly shows that only functions for adding unsigned, signed, natural, and integer are supported.

As @Tricky has stated in the comments, you need to define div as an unsigned.

There's also IEEE Std 1076-2008 package numeric_std_unsigned which treats std_logic_vector as type unsigned through encapsulation and providing the same functionality. — , Jul 01 '20 at 23:34
Indeed there is, but that is only compatible with VHDL-2008 and later. Most tools will default to VHDL-93 and I didn't want to confuse the issue with a discussion about this. — Vance, Jul 02 '20 at 09:37
@BananaGuy I'm not sure, a blue one I guess. Seriously though, in the context of your original question and my answer, your question in the comment doesn't make sense. — Vance, Jul 22 '20 at 10:05

Xilinx ISE: found '0' definitions of operator "+", cannot determine exact overloaded matching definition for "+"

1 Answers1