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Instantiate the following module connecting ports by name. The output of the module should be connected to wire S, port B should connect to wire T, and port C should also connect to wire T.

my_module(output A, input B, input C);

How can I write Verilog code for this?

Hassaan
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1 Answers1

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in verilog when connections are expressed by associating wires with ports or other variables. An example of instance connections follows. Wire T (input to the top module) is connected to ports B and C of the my_module from your example.

module top(output S, input T);
   my_module mminst(.A(S), .B(T), .C(T));
endmodule
Serge
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  • This is on Low Quality Posts review queue because you haven't added a description for what it does/how it works. Please edit and add text to avoid deletion. – clearlight Feb 27 '20 at 21:03