Good day! I have a following issue:
I am using Xilinx ISE 14.5 to design for a Spartan 6 FPGA. I noticed that is one of my designs I wasn't able to change the physical pin mapping for a signal. When I changed the line in the .ucf file to another physical pin, re-synthesized and re-implemented the design and uploaded new .bit file the actual signal was still being routed to the old pin.
After that I completely cleared the .ucf file and again rerun the synthesis, implementation etc. and the software didn't even give me a warning about the missing pin declarations.
Here's my code:
entity top is
port(
i_clk : IN STD_LOGIC;
o_test3 : INOUT STD_LOGIC := '1'
);
end top;
architecture Behavioral of top is
begin
p_test: process (i_clk) begin
if rising_edge(i_clk) then
o_test3 <= not o_test3;
end if;
end process;
end Behavioral;
enter code here
The .ucf file is completely empty. I expect the software to raise a warning about the missing declaration of i_clk and o_test3. Is my understanding wrong?
If it should raise a warning, is this a bug that can be helped? I am thinking of installing 14.7 version in hopes that it would fix the issue but I thought I'd ask about any possible solutions first. Thanks in advance.