Xilinx ISE is the toolchain package for programming Xilinx FPGAs in VHDL and Verilog.
Questions tagged [xilinx-ise]
291 questions
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VHDL synthesis error. Signal blk_pointer cannot be synthesized, bad synchronous description
I've got a problem with a synthesis of that code.
The error which is shown is "Signal blk_pointer cannot be synthesized, bad synchronous description. The description style you are using to describe a synchronous element (register, memory, etc.) is…
Bob Son
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2 answers
AXI bus to Wishbone Wrapper
Could anyone please tell me about the AXI bus and its signals. I would also want to know about AXI bus to wishbone bus wrapper to implement it in VHDL.
I am looking at the implementation of a register in FPGA and then give the corresponding…
Tech Geek
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2 answers
Getting error: localparam shift1 cannot be overwritten,however I declared as parameter in verilog
I have the following LFSR written in verilog:
module LFSR #(parameter SIZE=1) /*Define a parameter for size of output*/
(
input clk,
input reset,
output [SIZE-1:0] q
);
/*feedback taps for the LFSR*/
parameter…
user3716072
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Test Bench Waveform no longer on Xilinx....Need VHDL guidance
MAJOR UPDATE. NEVERMIND. I FOUND AN OLDER VERSION OF XILINX ISE SUITE IN THE FORM OF A TORRENT. THE OLDER VERSION HAS TEST BENCH WAVEFORM. I REALLY DISLIKE THEIR BUSINESS MODEL OF DISCONTINUING CERTAIN APPLICATIONS WHICH MAKE THE PROCESS EASIER.…
user3268215
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0
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2 answers
VHDL - unconnected components in top module
I am working on a project and I'm failing to connect the components in the top module.
I just can't see what I'm doing wrong. Any suggestions are highly appreciated.
Besides not being able to see the components in the RTL schematic, I get some…
Rui Moreno
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1 answer
Xilinx ISE 9.2i setup error
every time I try to setup Xilinx 9.2i the installation stops at 99% and a message appears from Windows says the program has stopped what should I do ?
Mohamed MosȜd
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3 answers
Change VHDL testbench and 32bit-ALU with clock to one without
I wrote this VHDL-program vor an ALU and its testbench that is working:
ALU-code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ALU_CLK is
port( Clk : in std_logic; --clock signal
InRegA,InRegB : in…
kimliv
- 427
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0
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1 answer
FF/Latch trimming
here's part of my Verilog code:
reg [5:0] channel[0:7];
reg [5:0] tmp[0:7];
reg [2:0] counter_out;
reg [2:0] scounter_samp;
reg [2:0] scounter_bits;
...
always @(posedge clk, posedge rst) begin
if(rst) begin
done <= 1'b0;
…
Dominik Szerszeń
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1 answer
where to check which dcm/pll supported in which xilinx fpga technology?
Please tell me where to look for supported DCM/PLL on xilinx fpga technology .
Example - DCM_ADV supported in virtex 4 but not in xcv5
Avinash Kumar
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votes
1 answer
how to write inverted clock signal in ucf?
Like - create_generated_clock [get_pins xyz] -source clk -divide_by 4 -invert
I need to convert sdc to ucf .
How to write -invert in UCF constraint ?
Avinash Kumar
- 739
- 2
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- 25
0
votes
1 answer
VHDL Process Confusion with Sensitivity Lists
I am learning VHDL by reading books online (Free Range VHDL), and imlementing the examples on my Nexsys2 via Xilinx ISE Webpack 14.7. I am re-reading the Free Range VHDL text and am currently in the chapter discussing processes. I have a solid…
radensb
- 664
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- 25
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1 answer
Generic driven customizable bus width on port of symbol
I've created a VHDL module in ISE and generated the corresponding schematic symbol. I would like the buses in the symbol to be variable width, specified using an attribute in the schematic layout editor. A whole-project DRC is okay, but when I…
MTCoster
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1 answer
Warning: It is ambiguous to apply a single loc constraint on multiple IO primitives; we will keep the constraint on the instance
I think I have some designing problem in VHDL.
I am trying to set some pin to high and low. to set another connected board.
I am getting the following warnings:
[Constraints 18-5] Cannot loc instance 'processing_system7_0_PS_PORB_IBUF' at site…
user3442775
-1
votes
1 answer
How to change a register value without adding it to the sensitivity list?
module main(input A, B, C,button,clk100mhz,output [7:0]seg,[7:0]an);
reg [3:0] D0;
reg [3:0] D1;
reg [3:0] D2;
reg [7:0] Y;
DISP7SEG m1 (clk100mhz, D0, D1, D2, 4'b0000,4'b0000,4'b0000,4'b0000,4'b0000, 1'b0, 1'b0, 1'b0,1'b0,1'b0,…
testtest123321
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-1
votes
1 answer
Find Maximum Number present in Verilog array
I have tried writing a small verilog module that will find the maximum of 10 numbers in an array. At the moment I am just trying to verify the correctness of the module without going into specific RTL methods that will to do such a task.
I am just…
Arslan Majid
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