Stack Overflow
Stack Overflow

Questions tagged [xilinx-ise]

Xilinx ISE is the toolchain package for programming Xilinx FPGAs in VHDL and Verilog.

291 questions
0
votes
1 answer

How to prevent ISE compiler from optmizing away my array?

I'm new to Verilog, ISE, FPGAs. I'm trying to implement a simple design into an FPGA, but the entire design is being optimized away. It is basically an 2D array with some arbitrary values. Here is the code: module top( output reg out ); integer…
Luis Filipe Martins Barros
  • 167
  • 1
  • 1
  • 7
0
votes
1 answer

Exit a loop using external signal in VHDL

I am trying to write a block of data (16 bytes, 4 words) from my entity cache to my other entity memory. The memory is byte addressable, so I can write only 1 byte at a time. The memory will update mem_done to 1 when a byte has been written. To…
JahMyst
  • 1,616
  • 3
  • 20
  • 39
0
votes
0 answers

UART communication using the Atlys board with a computer running a Terminal program

I want to connect an hyper terminal to an Atlys Spartan-6 xc6slx45 FPGA,I follow a tutorial which I found on youtube.But when I press a button the screen of hyper terminal still clear.The board is well connected to the PC.
Classe Ensi E
  • 45
  • 2
  • 10
0
votes
0 answers

moving block ram files in xilinx ISE

I have a question regarding Xilinx block-ram files. I am working with a group of people on a project. When one person generates a block ram another group member migrates the block_ram.xco, and block_ram.vhd files into their project, and adds the…
Logan
  • 1
0
votes
1 answer

$rtoi() is not a constant system function

I want to set size of a constant for a counter: localparam MAX_COUNT = ((debounce_per_ms * clk_freq)) + 1; parameter MAX_COUNT_UPPER = $rtoi($floor($log10(MAX_COUNT)/$log10(2))); That work well with XST (ise) and with verilator but in Icarus I've…
FabienM
  • 3,421
  • 23
  • 45
0
votes
1 answer

How to constrain a counter reg size in verilog for ise synthesis?

I want to declare a counter reg in function of some parameters. I did it in this way : parameter clk_freq = 95000; // clock frequency in kHz parameter debounce_per_ms = 20; localparam MAX_COUNT = ((debounce_per_ms * clk_freq)) + 1; reg…
FabienM
  • 3,421
  • 23
  • 45
0
votes
1 answer

Xilinx ISE Project Navigator(nt64) and MVS2010

After "Generate programming file" for a easy FPGA LED project using the Xilinx 14.7 ISE (nt64) I got the following error: Started : "Map". Running map... Command Line: map -intstyle ise -p xc6slx45-csg484-2 -w -logic_opt off -ol high -t 1 -xt 0…
Hank81
  • 43
  • 1
  • 4
0
votes
1 answer

How to improve default execution speed in Xilinx ISE?

I was trying to implement a 1Hz clock using 100MHz clock. However, In the xilinx ISE, ISIM execution speed is around 5ms per second. This is too slow for my project. How do I modify default execution speed?
Peter Hwang
  • 971
  • 1
  • 12
  • 25
0
votes
0 answers

Specifying hold time for flip-flop in Xilinx ISE user constraints file

I have written a simple D-type flip flop using VHDL and am sythesizing it in Xilinx ISE. I wish to specify the setup and hold times. In my user constraints file I put the line: TIMEGRP "D" OFFSET = IN 10 ns VALID 10 ns BEFORE "clk" RISING; Am I…
epsilon_j
  • 325
  • 4
  • 14
0
votes
1 answer

VHDL simulation failed with unexpected result

I learned VHDL 5 years back, and never used after that as I was working on different domain. Now I'm working in a project that required some work in VHDL. I have to implement SPI to program a ADF4158 device. I opened a book for syntax and tried to…
dDebug
  • 57
  • 1
  • 1
  • 8
0
votes
1 answer

XXX on output ports

I have written an asynchronous fifo buffer but when I run it I get XXX on output ports. I referred to concerned questions on SO which said asserting reset signals should make it work but despite of doing it I am still facing the same issue. Any help…
prerna B
  • 45
  • 1
  • 2
  • 7
0
votes
1 answer

GHDL: How do I bind components?

I'm running automated testbenches with ghdl (0.32rc1). Some of my testbenches require unisim primitives from Xilinx ISE. I have prepared two external files, if one would like to test my example. To run my example, you'll need a Xilinx ISE or Vivado…
Paebbels
  • 15,573
  • 13
  • 70
  • 139
0
votes
2 answers

HDLParsers:800 Type of "**" is incompatible with type of "**"

entity address_decoder is PORT(address : in STD_LOGIC_VECTOR ( 0 to 3 ); decoded_address : out integer range 0 to 15); end address_decoder; architecture dataflow of address_decoder is begin PROCESS(address) begin if address = "0000" then…
vineel13
  • 3
  • 2
0
votes
1 answer

Why dynamic power consumption is always zero?

I want to get an accurate power report that contains real dynamic and static power consumption. I'm working on Xilinx spartan3 board. My code has no errors but after selecting the "Generate Text Power Report" in ISE (Xilinx synthesis tool), always…
Amir
  • 507
  • 3
  • 12
0
votes
1 answer

How do I update coe data in ISE?

I've got a simple project in ISE (Webpack) that consists of ROM block that I'm filling with data from a coe file. If I edit that file with an external application (notepad, say) then how do I get the changes to propagate through to my design…
Mark Feldman
  • 15,731
  • 3
  • 31
  • 58
1 2 3
…
19 20