MAJOR UPDATE. NEVERMIND. I FOUND AN OLDER VERSION OF XILINX ISE SUITE IN THE FORM OF A TORRENT. THE OLDER VERSION HAS TEST BENCH WAVEFORM. I REALLY DISLIKE THEIR BUSINESS MODEL OF DISCONTINUING CERTAIN APPLICATIONS WHICH MAKE THE PROCESS EASIER.
My issue is that I am working a Simple Machine Schematic Circuit which and trying to display is waveform under certain conditions. However Im using the latest Xilinx ISE which does not have Test Bench Waveform ( i cant seem to download old version on Windows 8.1).
I have been struggling to learn the correct VHDL. This is the generated VHDL that I have.
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY UNISIM;
USE UNISIM.Vcomponents.ALL;
ENTITY top_top_sch_tb IS
END top_top_sch_tb;
ARCHITECTURE behavioral OF top_top_sch_tb IS
COMPONENT top
PORT( Q1 : OUT STD_LOGIC;
RCO : OUT STD_LOGIC;
INPUT : IN STD_LOGIC;
PRE : IN STD_LOGIC;
CLK : IN STD_LOGIC;
Q0 : OUT STD_LOGIC);
END COMPONENT;
SIGNAL Q1 : STD_LOGIC;
SIGNAL RCO : STD_LOGIC;
SIGNAL INPUT : STD_LOGIC;
SIGNAL PRE : STD_LOGIC;
SIGNAL CLK : STD_LOGIC;
SIGNAL Q0 : STD_LOGIC;
BEGIN
UUT: top PORT MAP(
Q1 => Q1,
RCO => RCO,
INPUT => INPUT,
PRE => PRE,
CLK => CLK,
Q0 => Q0
);
-- *** Test Bench - User Defined Section ***
tb : PROCESS
BEGIN
WAIT; -- will wait forever
END PROCESS;
-- *** End Test Bench - User Defined Section ***
END;
These were the conditions that I was going to use test bench for...but need a VHDL equivalent.
Open the HDL Bencher window. In the Initialize Timing window, select the option Single Clock. Set Clock High Time and Clock Low Time to 50 ns, Input Setup Time and Output Valid Delay to 10 ns, and Initial Length of Test Bench to 2500 ns. After checking the values, click on Finish.
I have found different VHDL language sites... but I cant really clarify anything. IF more detail is needed I will try to supply it.
