Warning: It is ambiguous to apply a single loc constraint on multiple IO primitives; we will keep the constraint on the instance

Question

I think I have some designing problem in VHDL.

I am trying to set some pin to high and low. to set another connected board.

I am getting the following warnings:

 [Constraints 18-5] Cannot loc instance 'processing_system7_0_PS_PORB_IBUF' at site B5, Site location is not valid [D:/Sensor/receiver/receiver.srcs/sources_1/edk/module_1/implementation/module_1_processing_system7_0_wrapper.ncf:137]

 [Constraints 18-5] Cannot loc instance 'processing_system7_0_PS_SRSTB_IBUF' at site C9, Site location is not valid [D:/Sensor/receiver/receiver.srcs/sources_1/edk/module_1/implementation/module_1_processing_system7_0_wrapper.ncf:138]

 [Constraints 18-5] Cannot loc instance 'processing_system7_0_PS_CLK_IBUF' at site F7, Site location is not valid [D:/Sensor/receiver/receiver.srcs/sources_1/edk/module_1/implementation/module_1_processing_system7_0_wrapper.ncf:139]

 [Designutils 20-1397] We found multiple IO primitives connected to net 'module_1_i/receiver_0_rs_uart_out_pin'. It is ambiguous to apply a single loc constraint on multiple IO primitives; we will keep the constraint on the instance 'module_1_i/receiver_0/XST_VCC' driving the net 'module_1_i/receiver_0_rs_uart_out_pin'. [D:/Sensor/receiver/receiver.srcs/sources_1/edk/module_1/data/module_1.ncf:5]

 [Constraints 18-5] Cannot loc instance 'module_1_i/receiver_0/XST_VCC' at site J15, Unknown instance type 'VCC' [D:/Sensor/receiver/receiver.srcs/sources_1/edk/module_1/data/module_1.ncf:5]

 [Designutils 20-1397] We found multiple IO primitives connected to net 'module_1_i/receiver_0_rs_te_485_pin'. It is ambiguous to apply a single loc constraint on multiple IO primitives; we will keep the constraint on the instance 'module_1_i/receiver_0/XST_GND' driving the net 'module_1_i/receiver_0_rs_te_485_pin'. [D:/Sensor/receiver/receiver.srcs/sources_1/edk/module_1/data/module_1.ncf:6]

 [Constraints 18-5] Cannot loc instance 'module_1_i/receiver_0/XST_GND' at site J16, Unknown instance type 'GND' [D:/Sensor/receiver/receiver.srcs/sources_1/edk/module_1/data/module_1.ncf:6]

 [Designutils 20-1397] We found multiple IO primitives connected to net 'module_1_i/receiver_0_rs_hf_out_pin'. It is ambiguous to apply a single loc constraint on multiple IO primitives; we will keep the constraint on the instance 'module_1_i/receiver_0/XST_VCC' driving the net 'module_1_i/receiver_0_rs_hf_out_pin'. [D:/Sensor/receiver/receiver.srcs/sources_1/edk/module_1/data/module_1.ncf:7]

 [Constraints 18-5] Cannot loc instance 'module_1_i/receiver_0/XST_VCC' at site L17, Unknown instance type 'VCC' [D:/Sensor/receiver/receiver.srcs/sources_1/edk/module_1/data/module_1.ncf:7]

 [Designutils 20-1397] We found multiple IO primitives connected to net 'module_1_i/receiver_0_rs_rxen_bar_pin'. It is ambiguous to apply a single loc constraint on multiple IO primitives; we will keep the constraint on the instance 'module_1_i/receiver_0/XST_GND' driving the net 'module_1_i/receiver_0_rs_rxen_bar_pin'. [D:/Sensor/receiver/receiver.srcs/sources_1/edk/module_1/data/module_1.ncf:8]

 [Constraints 18-5] Cannot loc instance 'module_1_i/receiver_0/XST_GND' at site N17, Unknown instance type 'GND' [D:/Sensor/receiver/receiver.srcs/sources_1/edk/module_1/data/module_1.ncf:8]

 [Designutils 20-1397] We found multiple IO primitives connected to net 'module_1_i/receiver_0_rs_dxen_pin'. It is ambiguous to apply a single loc constraint on multiple IO primitives; we will keep the constraint on the instance 'module_1_i/receiver_0/XST_VCC' driving the net 'module_1_i/receiver_0_rs_dxen_pin'. [D:/Sensor/receiver/receiver.srcs/sources_1/edk/module_1/data/module_1.ncf:9]

 [Constraints 18-5] Cannot loc instance 'module_1_i/receiver_0/XST_VCC' at site M15, Unknown instance type 'VCC' [D:/Sensor/receiver/receiver.srcs/sources_1/edk/module_1/data/module_1.ncf:9]

The code part which is causing these warnings is might be this: I have an IP in EDK project: which has two files: reciever.vhd and user_logic.vh. In the user_logic.vhd I made some out ports and I am trying to assign high and low values to those ports.

    entity user_logic is
      port
      (

            rs_rx           : in  std_logic;
            rs_clk_in       : in  std_logic;
            rs_dxen             : out std_logic;
            rs_uart_out     : out std_logic;
            rs_hf_out       : out std_logic;
            rs_rxen_bar     : out std_logic;
            rs_te_485       : out std_logic;
                    Bus2IP_Resetn                  : in  std_logic;

      );
architecture IMP of user_logic is
    signal q : unsigned(9 downto 0) := (others => '0');
    signal rx_clk : std_logic := '0' ;

    signal  rs_dxen_i      : std_logic;
    signal  rs_uart_out_i  : std_logic;
    signal  rs_hf_out_i     : std_logic;
    signal  rs_rxen_bar_i   : std_logic;
    signal  rs_te_485_i     : std_logic;

begin

    rs_dxen  <= rs_dxen_i;
    rs_uart_out <= rs_uart_out_i;
    rs_hf_out <= rs_hf_out_i;
    rs_rxen_bar <= rs_rxen_bar_i;
    rs_te_485 <= rs_te_485_i;

    process ( Bus2IP_Resetn, rs_clk_in ) is 

    begin 

        if(Bus2IP_Resetn = '1') then

            rs_dxen_i  <= '1';
            rs_uart_out_i <= '1';
            rs_hf_out_i <= '1';
            rs_rxen_bar_i <= '0';
            rs_te_485_i <= '0';

    elsif rs_clk_in'event and rs_clk_in = '1' then

    q <= q + 1;

    rx_clk <= q(9);   --- 58.gdfg/2^9=~ 115.82Khz baud rate = 115200 


    end if;
   end process;

I make these ports external ports and connect to some pins. But I receive the warnings I mentioned above and I am not able to set the corresponding pins to high and low. But If in the code I don't assign any values to the out ports the warnings doesn't come.

warning for B5, C9 nad F7 can be ignored. three warning always comes. The other warning doesn't comes if I not put this part after begin: rs_dxen <= rs_dxen_i; rs_uart_out <= rs_uart_out_i; rs_hf_out <= rs_hf_out_i; rs_rxen_bar <= rs_rxen_bar_i; rs_te_485 <= rs_te_485_i;

score 0 · Answer 1 · answered May 22 '14 at 11:30

0

The VHDL is fine. The apparent problem is that the pin mappings are invalid.

The first thing I'd suspect is that the pin mappings belong to a different variant of the FPGA, so that e.g. B5, C9 and F7 do not have input buffers because these are power supply pins in this variant, or something similar.

The unknown instance type 'GND' is suspicious though.

answered May 22 '14 at 11:30

Simon Richter

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warning for B5, C9 nad F7 can be ignored. three warning always comes. The other warning doesn't comes if I not put this part after begin: rs_dxen <= rs_dxen_i; rs_uart_out <= rs_uart_out_i; rs_hf_out <= rs_hf_out_i; rs_rxen_bar <= rs_rxen_bar_i; rs_te_485 <= rs_te_485_i; – May 22 '14 at 11:32
If you don't drive the outputs at all, these are optimized out during netlist generation, which makes the invalid pin mappings irrelevant. – Simon Richter May 22 '14 at 12:43
ok. So I have to drive these output pins to 1 and 0. how do I do this? Earlier I was using planahead, Now I tried the same code using xilinx ISE and it works the output ports are high but there is one problem that in my code I put some pins to 1 and some to zero. but all the pins are set to high when I checked the pins on the oscilloscope. – May 22 '14 at 13:53
As said, the VHDL is fine, but the pin mapping isn't. Because of the faulty mapping, the signals you set in the VHDL code aren't routed to the outside, which is why you don't see the expected levels. – Simon Richter May 22 '14 at 14:08
I've retagged the question, because the pin mapping is toolchain dependent, and we need a Xilinx ISE expert in here, which I'm not. – Simon Richter May 22 '14 at 14:11
Is it possible to the pins to high and low using the net_vcc and net_gnd in the mhs file. I tried that for one board it worked fine but for ynq 7000 series t doesn't works. Is there any other method to set the pins to high and low ? – May 23 '14 at 00:21
If I understood correctly, `NET_VCC` is the actual power supply, and only power supply pins should be assignable to that net. – Simon Richter May 23 '14 at 08:27

Warning: It is ambiguous to apply a single loc constraint on multiple IO primitives; we will keep the constraint on the instance

1 Answers1