Questions tagged [object-test-bench]
12 questions
4
votes
3 answers
How to get Visual Studio 2008 Object Test Bench to work?
I'd like to use the Object Test Bench in VS2008. The docs - and even the helpful text in the test bench window - say to right click on class in the Class View. Further reading indicates that this class must be in the startup project or referenced…
Jon B
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2
votes
2 answers
Testbench for T Flip Flop using D Flip Flop in VHDL
I have VHDL codes that of a D Flip Flop, and a T Flip Flop that uses it structurally: it consists of a DFF with D input being T Xored with Q, a clock. But my simulation gives me a waveform that has an output of only a red straight line 'U'. I think…
Rawan Moukalled
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2
votes
3 answers
Is the Visual Studio 2008 Object Test Bench useful for anything?
Is the Visual Studio 2008 Object Test Bench useful for anything? Maybe I'm missing something but aside from a flashy version of the immediate window, it doesn't seem like a developer would actually use it for anything.
(And how many people knew…
Dan Esparza
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0
votes
1 answer
How to manage reset signal for VHDL test benches?
I have a very simple vhdl testbench that should run.
My components all have a reset signal, so that registers are set to 0 and other components correctly initialized... but... if I create a common signal for resetting all component only during the…
Andry
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0
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1 answer
Systemverilog Testbench how to deal with configurable number of interfaces
I have a design to verify. The design is similar to a network router. It has a number of FIFO input interfaces and a number of FIFO output interfaces. So the same group of interfaces will repeat over and over.
DUT example:
module router(
input…
Shuo
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0
votes
1 answer
Iverilog help combinational shift multiplier
My code compiles but does not dump any dat file for gtkwave. I'm trying to implement a combination shift multiplier object. I don't think my tester is correct.
module combinational_mult(product,multiplier,multiplicand);
input [31:0] multiplier;
…
MC22
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0
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0 answers
Test Bench Waveform no longer on Xilinx....Need VHDL guidance
MAJOR UPDATE. NEVERMIND. I FOUND AN OLDER VERSION OF XILINX ISE SUITE IN THE FORM OF A TORRENT. THE OLDER VERSION HAS TEST BENCH WAVEFORM. I REALLY DISLIKE THEIR BUSINESS MODEL OF DISCONTINUING CERTAIN APPLICATIONS WHICH MAKE THE PROCESS EASIER.…
user3268215
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0
votes
0 answers
How to write a string (send) stimulus markers in e-prime for correct and incorrect responses
Hello I need help with sending an alphanumeric marker when presenting a stimulus. I have set the port for communication and already have successfully sent markers to another program.
My wish now is to send markers if stimuli are correct or…
0
votes
1 answer
verilog testbench - submodule array writing in a file
I need to write an array in a file in verilog test bench. the array is declared as below in the module stage1.v (hierarchy picture attached)
wire [WIDTH-1:0] s1_res1_arr[0:LENGTH-1];
it is filled with certain values.
in my testbench i am writing…
user3056350
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0
votes
2 answers
VHDL State Machine testbench
Description:
I am trying to generate a test bench for a 5 state sequential state machine that detects 110 or any combination of (2) 1's and (1) 0. I already have written the code. see below. I am having trouble with the test bench which is wrong.…
user2444074
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0
votes
1 answer
VHDL Simulation Stopping by itself
I dont get this, simulation just stops after "taster" signal becomes "1", no idea why. In Xilinx IDE package testbench.
entity komb is
Port ( reset : in STD_LOGIC;
clk : in STD_LOGIC;
levo_ndesno : in STD_LOGIC;
…
Vidak
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0
votes
2 answers
Importing C functions in System Verilog with file-type Argument
I am trying to import a C function into a System verilog test bench. The code for the C function is as shown below. I want to pass files as arguments. The function basically reads from one file and writes to another.
int readmem(int z, FILE…
Vikram M Kale
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