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I use Xilinx system generator blocks in Matlab and i find the block black box wich can generate and simulate vhdl code. I programme a simple program in vhdl for port and,

--import std_logic from the IEEE library
library ieee;
use ieee.std_logic_1164.all;

--ENTITY DECLARATION: name, inputs, outputs
entity andGate is                   
   port( A, B : in std_logic;
            F : out std_logic);
end andGate;

--FUNCTIONAL DESCRIPTION: how the AND Gate works
architecture func of andGate is 
begin
  F <= A and B;     
end func;

I simulate in xilinx with blackbox and i make simulation mode ISE Simulator because i use xilinx .

I apreciate any kind of help thanks :)

Marie
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  • Could you be more clear on what your issue is? – brodoll May 11 '15 at 18:18
  • Thanks fr your reply , i use blackbox from xilinx system generator on matlab but an erroe message ''Error reported by S-function 'sysgen' in 'essai1/Black Box':An internal error occurred in the Xilinx Blockset Library.''I don't know the reason my code in vhdl is posted thankss how can i use blackbox ?? is there is any specificity thankss – Marie May 11 '15 at 18:20
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    This is mainly a statement, could you at least describe a problem you are trying to solve ? –  May 11 '15 at 18:20
  • Is there is anyone who used the block blackbox from matlab xilinx système generator ?? – Marie May 11 '15 at 18:24

1 Answers1

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check your gateway in, you should select its output as Boolean

also, check the sampling time of the system, you should make all equal to 1

Serwan Bamerni
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  • This could be a comment not a an answer. You can add more description to make it a good answer - [From Review](http://stackoverflow.com/review/late-answers/12348467) – Raju May 14 '16 at 02:21