XILINX ISE set I/O Marker as Clock

Question

I'm on Xilinx ISE IDE and using the Schematic Editor.

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The constraints file is following:

NET "A" LOC = M18;
NET "F" LOC = P15;
NET "B" LOC = M16;


NET "A" PULLUP;
NET "B" PULLUP;
NET "F" DRIVE = 8;

But when I want to compile my program, there is this error:

ERROR:Place:1108 - A clock IOB / BUFGMUX clock component pair have been found
   that are not placed at an optimal clock IOB / BUFGMUX site pair. The clock
   IOB component <B> is placed at site <M16>. The corresponding BUFG component
   <B_BUFGP/BUFG> is placed at site <BUFGMUX_X2Y3>. There is only a select set
   of IOBs that can use the fast path to the Clocker buffer, and they are not
   being used. You may want to analyze why this problem exists and correct it.
   If this sub optimal condition is acceptable for this design, you may use the
   CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message to a
   WARNING and allow your design to continue. However, the use of this override
   is highly discouraged as it may lead to very poor timing results. It is
   recommended that this error condition be corrected in the design. A list of
   all the COMP.PINs used in this clock placement rule is listed below. These
   examples can be used directly in the .ucf file to override this clock rule.
   < NET "B" CLOCK_DEDICATED_ROUTE = FALSE; >
ERROR:Pack:1654 - The timing-driven placement phase encountered an error.

How to fix it?

What is the name of your FPGA board? Your clock pin location is not optimal. — Paebbels, Jul 19 '15 at 13:23

score 1 · Answer 1 · answered Jul 19 '15 at 13:37

While any signal can theoretically be used as a clock, it's not true for FPGA; at least not optimally. Clocks need special considerations that translate to restriction on which pin of the FPGA can be routed to the clock network.

I suspect that in your case, you used a push-button to act as a clock signal, which will only work on a very small design (like yours) because of debouncing and the fact that it's not a clock-enabled input port.

You can tell the tool that you want the sub-optimal and potentially erroneous clock path by adding the following constraint to your .ucf:

NET "B" CLOCK_DEDICATED_ROUTE = FALSE;

Keep in mind that you shouldn't do that without being sure that your design is fine with it... I recommend that you do further design with a "real" clock connected to a clock port on your FPGA, every board has one. That constraint will make your design work, but in a larger, faster design is likely to be a source of problems.

XILINX ISE set I/O Marker as Clock

1 Answers1