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I am trying to make an ALU for floating point numbers.This is my code and whenever I try to run simulation of a testbench waveform simulator crashes stating this:

isim_beh.exe has stopped working

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity fp is
port( in_one:in std_logic_vector(31 downto 0);
        in_two:in std_logic_vector(31 downto 0);
        select_line:in std_logic_vector(2 downto 0);
        output:out std_logic_vector(31 downto 0));
end fp;

architecture Behavioral of fp is
signal bb:std_logic_vector(31 downto 0);
signal j,k,l:std_logic_vector(31 downto 0);
component floating 
port (ina,inb:in std_logic_vector(31 downto 0);
        sss:in std_logic_vector(2 downto 0);
        outb:out std_logic_vector(31 downto 0));
end component;
component adder
port( a:in std_logic_vector(31 downto 0);
        b:in std_logic_vector(31 downto 0);
        sss:in std_logic_vector(2 downto 0);
        oo:out std_logic_vector(31 downto 0));
end component;
begin
u1:floating port map(in_one,in_two,select_line,j); --When ss=10 then     multiply is chosen
u2:adder port map(in_one,in_two,select_line,k);     --When ss=00 then addition is chosen and when ss=01 then subtraction is chosen
output<=(not in_one) when select_line="100" else
          (in_one and in_two) when select_line="101" else
          (in_one or in_two) when select_line="110" else
          j+k;
end Behavioral;

PS Floating is the component for multiplication. Adder is the component for addition and subtraction.

Qiu
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Arslan
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  • You could try with another VHDL implementation. They seldom have identical errors, you might find a tool that produces a useful error message. Reminds me of [generic adder “inference architecture”: simulation error](http://stackoverflow.com/questions/30020402/generic-adder-inference-architecture-simulation-error). Your code isn't complete enough for someone else to reproduce the problem (or not). –  May 08 '15 at 11:37
  • What are the other tools that can be used here. And also they should be freeware also because I wont be able to purchase them just for single simulation. – Arslan May 08 '15 at 11:43
  • ghdl comes to mind. You could also try writing testbenches for your your two instantiated components to divide and conquer the problem. It's either in your top level (shown), it's testbench or one of the two instantiated components (not shown). You should be able to narrow it down. –  May 08 '15 at 11:48

0 Answers0