Highest Voted 'xilinx-ise' Questions

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Warnings while synthesising, not able to run ISim

module SimpleDDS(DAC_clk, DAC_data); input DAC_clk; output [9:0] DAC_data; // let's create a 16 bits free-running binary counter reg [15:0] cnt; always @(posedge DAC_clk) cnt <= cnt + 16'h1; // and use it to generate the DAC signal output wire…

verilog xilinx xilinx-ise

asked Jan 31 '17 at 14:28

prakash Sri

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3 answers

Xilinx device specific primitives

I need a list of device-specific primitives of Xilinx devices. I know that ISE has a list of templates and there are also PDF user guides but I need them as list of files in a folder so that I can parse them and extract name and port-list of every…

vhdl verilog xilinx xilinx-ise

asked Jan 20 '17 at 08:07

Laleh

465
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1 answer

Specifying the Rise and Fall Time for clocks

I am trying to simulate a D-Flip Flop for Metastability. With ideal clocks generation in Xilinx ISE and Vivado, I cannot see the metastability phenomenon. I need to specify the clock with Rise and Fall time for the metastability to occur. I couldn't…

verilog xilinx-ise vivado

asked Jan 15 '17 at 06:37

Swastika

51
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1 answer

How to use sequential statements (e.g. process) to make constant value but without wait?

For the sake of consistency and ease of maintenance, I would like to make some constants using sequential statements, e.g. in process. I have defined a range using: subtype FIELD is natural range 3 downto 0; A process that makes the value could…

vhdl xilinx xilinx-ise

asked Dec 14 '16 at 11:09

EquipDev

5,573
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1 answer

Synthesize error in std_logic_vector to integer conversion [ERRORS: HDLParsers: 854]

count := to_integer( unsigned ( values(i))); Error: ERRORS: HDLParsers: 854 - The expression can not be converted to type unsigned Preconditions: imports library ieee; use ieee.std_logic_1164.all; use ieee.math_real.all; count declared as…

vhdl fpga xilinx xilinx-ise

asked Nov 28 '16 at 09:50

Davide Pimpinella

11
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2 answers

Combining `others` expression with `signed` cast

Let var stand for a signed vector (library IEEE.NUMERIC_STD.ALL) of size m. Let foo be another variable of type std_logic_vector(n-1 downto 0), where n is smaller than m. I want to concatenate a '0' left of foo, then pad it with zeroes in its right…

vhdl xilinx-ise

asked Nov 26 '16 at 19:34

Jsevillamol

2,425
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1 answer

How to add clock in Xilinx/Verilog

I am new in Xilinx. Here's my code,and i want to add clock in it. Please tell me how to add clock. Thanks code module Traffic( output reg red1, output reg red2, output reg red3, output reg red4, output reg yel1, output reg…

verilog xilinx-ise

asked Nov 19 '16 at 18:20

Ahmed Saeed

21
3

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1 answer

Verilog, Module Instantiation with inputs from different modules

Module's Hierarchy where uart_receiver.v=ModuleA, RSD.v=ModuleB, uart_transmitter.V=ModuleC Suppose I want to Instantiate ModuleA with inputs from different modules, B, and the name of inputs are: WR_EN from moduleB and RD_EN, DT from…

module verilog instantiation xilinx-ise

asked Nov 08 '16 at 23:26

trakis95

23
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1 answer

Algorithm for Divison

I have been using '/' operator to perform divison in verilog. I am able to get the simulation results right but the thing is that my code was unable to get synthesized due to '/' operator. It was displaying the error "second operand of / should be a…

verilog xilinx-ise

asked Oct 28 '16 at 19:43

Vineeth Ananthula

85
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error: 'timezone' was not declared in time.h

Real simple program: #include main() { timezone; } The compile error I'm getting: error: 'timezone' was not declared in this scope On my Ubuntu machine this program compiles just fine using the standard time.h that looks just like…

c++ xilinx-ise

asked Oct 27 '16 at 22:43

Mike S

11,329
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2 answers

Using Generate Block/ Loop to Make a Ripple Carry Adder

I've already done searches here and found some insight, but some of the concepts about using this kind of loop elude me. Here are my modules for the Half-Adder and Full-Adder: module HalfAdder( A, B, Cout, S ); input A, B; output Cout, S; …

loops for-loop verilog xilinx-ise

asked Sep 11 '16 at 03:49

rub3z

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4 answers

change xilinx ise default text editor to notepad++

I want to add custom editor to Xilinx ISE project nevigator. How change xilinx ise default text editor to notepad++?

notepad++ xilinx-ise

asked Aug 07 '16 at 08:23

HosseinBeheshti

125
2
10

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votes

1 answer

Not able to write the output of testbench to file

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.NUMERIC_STD.ALL; use IEEE.STD_LOGIC_ARITH.all; use IEEE.STD_LOGIC_SIGNED.all; use std.env.all; USE IEEE.STD_LOGIC_TEXTIO.ALL; USE STD.TEXTIO.ALL; ENTITY tb_top IS END tb_top; ARCHITECTURE…

vhdl xilinx-ise

asked Jul 19 '16 at 17:38

Shrinivas Iyengar

21
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1 answer

How to generate .xst file from command line + Xilinx-ISE

I am trying to learn how to generate bit files from command line. Is there a way to generate the .xst script file from command line tools? I can only find mention of it being something that the GUI auto-generates. To add some context, I build and…

xilinx xilinx-ise

asked Jun 08 '16 at 15:00

Nick

862
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2 answers

Detecting rising edge synchronization of 2 different clocks

How do you detect rising edge synchronization of 2 different clocks(different frequencies) in VHDL programming using Xilinx software? There is a main clock of frequency 31.845 Mhz , and another clock of frequency 29.972 Mhz. So the basic aim is to…

vhdl edge-detection xilinx-ise

asked Jun 03 '16 at 08:24

KVK

1
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Questions tagged [xilinx-ise]