Detecting rising edge synchronization of 2 different clocks

Question

How do you detect rising edge synchronization of 2 different clocks(different frequencies) in VHDL programming using Xilinx software?

There is a main clock of frequency 31.845 Mhz , and another clock of frequency 29.972 Mhz. So the basic aim is to trigger an action when there is synchronization between the rising edges of 2 clocks. We tried implementing it using flipflops but we could achieve only Level synchronization, not Edge sync.

And we cannot compare the rising edges of 2 different clocks in statements like IF and WAIT in vhdl, So that is out of question.

We are trying to count pulses using a counter. For that, we need to stop the count whenever edge matching takes place. We are trying to implement a method called 'Vernier Interpolation'.

1. Initially, we used the following statement code, but since rising edges of 2 different clocks (clk0, clk1) cannot be compared in an IF statement, we had to drop it.

   if(rising_edge(clk0)=rising_edge(clk1)) then wait;

2. We then tried using WAIT statements (wait until) but it failed.

3. Then we tried using flipflops and delay circuits (D flipflop), but it resulted in level sync, and not Edge sync.

Answer 1

Firstly I'm not sure why you would want to do this. What you will get out is a new clock at the beat frequency between the two clocks.

The correct way to do this is to sample both clocks using another clock which is at least twice the frequency of the highest expected input. You could generate this higher clock using one of the PLLs in the device. x2 is a minimum. Ideally use a clock which is much higher than both sampled clocks.

Remember VHDL is not a language, it a description of synthesis of real hardware. So just saying Rising_Edge(clk1) = Rising_Edge(clk2) does not make the 'software' detect edges. All the function Rising_Edge really does is to tell the hardware to connect the clk signal to the clock input of a flipflop.

The proper solution is sample both 'clocks' in a process which is clocked by the a sample clock, look for edges (an edge being two subsequent samples that are different) then AND the result and latch if required.

sample code (untested, sorry no time right now).

entity twoclocks is
 port (
    op : out std_logic;
    clk1 : in std_logic;
    clk2 : in std_logic;
    sample_clk : in std_logic);
end entity;


architecture RTL of twoclocks is

begin

process sample(sample_clock, clk1, clk2):
begin
    if rising_edge(sample_clock):
      clk1_d <= clk1;
      clk2_d <= clk1;
      if clk1_d != clk1 and clk2_d != clk2 then
        op <= '1';
      else
        op <= '0';
      end if;
    end if;
end process;

end architecture;

Answer 2

The kind of vernier interpolator you want needs to be build using very tight timing constraints, thus you can probably not make it using VHDL alone. You need (a lot of) device specific constraints on resource locations and timing.

Please check out the work by A.Aloisio et al.. Aloisio and colleagues have build a vernier interpolator using specific Xilinx delay elements.

Standard VHDL synthesis is mostly suited for register transfer level descriptions. I.e. clocked/synchronous logic. But to compare these two inputs, you would need to sample them at a frequency of the least common multiple of both frequencies. For 31.845 MHz and 29.972 MHz that is a whopping 954.458340 MHz, which is a lot. I have seen these kind of speeds in FPGA logic though. ... But I'm thinking you might even need to double that, due to Nyquist. Maybe FPGA logic can nowadays handle 2 GHz swichting rate. But I'm not sure.

It might be possible to utilize a GT transceiver for this, but since that would be non-standard use of a such a transceiver, it might be hard to realize.