Warnings while synthesising, not able to run ISim

Question

module SimpleDDS(DAC_clk, DAC_data);
input DAC_clk;
output [9:0] DAC_data;

// let's create a 16 bits free-running binary counter
reg [15:0] cnt;
always @(posedge DAC_clk) cnt <= cnt + 16'h1;

// and use it to generate the DAC signal output
wire cnt_tap = cnt[7];     // we take one bit out of the counter (here bit 7 = the 8th bit)
assign DAC_data = {10{cnt_tap}};   // and we duplicate it 10 times to create the 10-bits DAC value 
                                     // with the maximum possible amplitude
endmodule

WARNING:Xst:2677 - Node of sequential type is unconnected in block .

WARNING:Xst:2677 - Node of sequential type is unconnected in block .

WARNING:Xst:2677 - Node of sequential type is unconnected in block .

WARNING:Xst:2677 - Node of sequential type is unconnected in block .

WARNING:Xst:2677 - Node of sequential type is unconnected in block .

WARNING:Xst:2677 - Node of sequential type is unconnected in block .

WARNING:Xst:2677 - Node of sequential type is unconnected in block .

WARNING:Xst:2677 - Node cnt_15 of sequential type is unconnected in block SimpleDDS.

Could someone help me out with this warning? I am not able to run ISim because of the same.

module test_SimpleDDs_v;

    // Inputs
    reg DAC_clk;

    // Outputs
    wire [9:0] DAC_data;

    // Instantiate the Unit Under Test (UUT)
    SimpleDDS uut (
        .DAC_clk(DAC_clk), 
        .DAC_data(DAC_data)
    );

    initial begin
        // Initialize Inputs
        DAC_clk = 0;

        // Wait 100 ns for global reset to finish
        #100;

        // Add stimulus here
        DAC_clk = ~ DAC_clk;
        #100;
        DAC_clk = ~ DAC_clk;
    end

endmodule

Focus on running the simulation first. In what way are you "not able" to run ISIM? — , Jan 31 '17 at 14:34
@BrianDrummond : i wrote a test bench which changes the clock but my square wave is not generated as expected, i get 'x' in all the cnt registers — prakash Sri, Jan 31 '17 at 20:51
Sounds like you're running ISIM just fine. How are you resetting `cnt` to a known value at the start of simulation? — , Jan 31 '17 at 21:06
i dont think i am resetting cnt to a know value, can u show me how? — prakash Sri, Jan 31 '17 at 23:34
` module test_SimpleDDs_v; // Inputs reg DAC_clk; // Outputs wire [9:0] DAC_data; // Instantiate the Unit Under Test (UUT) SimpleDDS uut ( .DAC_clk(DAC_clk), .DAC_data(DAC_data) ); initial begin // Initialize Inputs DAC_clk = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here DAC_clk = ~ DAC_clk; #100; DAC_clk = ~ DAC_clk; end endmodule` — prakash Sri, Jan 31 '17 at 23:35

score 0 · Answer 1 · answered Jan 31 '17 at 14:35

0

cnt[15:8] are unused. To eliminate those warning messages, just use an 8-bit counter.

reg [7:0] cnt;
always @(posedge DAC_clk) cnt <= cnt + 8'h1;

answered Jan 31 '17 at 14:35

toolic

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` module test_SimpleDDs_v; // Inputs reg DAC_clk; // Outputs wire [9:0] DAC_data; // Instantiate the Unit Under Test (UUT) SimpleDDS uut ( .DAC_clk(DAC_clk), .DAC_data(DAC_data) ); initial begin // Initialize Inputs DAC_clk = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here DAC_clk = ~ DAC_clk; #100; DAC_clk = ~ DAC_clk; end endmodule ` – prakash Sri Jan 31 '17 at 23:36

Warnings while synthesising, not able to run ISim

1 Answers1