Xilinx ISE is the toolchain package for programming Xilinx FPGAs in VHDL and Verilog.
Questions tagged [xilinx-ise]
291 questions
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How to write a byte in a 32bit wide Block RAM
I have a BLOCK RAM (single port ram) generated with the following parameters:
Memory Type: Single Port RAM
Write Enable: Use Byte Write Enable = Disabled
Write/Read Width = 32
Write/Read depth = 131072
and it is working fine.
Now I want to…
Sajjad
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1 answer
Shift Register or FIFO in block RAM (Xilinx)
I have to buffer some data in a quite big buffer. It is not a usual shift register or a FIFO, because I will have to be able to read data also from the middle of the buffer.
I managed to implement that in a way so I can use it as I need it. The…
ARude
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1 answer
How to rename the .mcs output file when synthesizing a design with Xilinx ISE
When I synthesize a design using Xilinx ISE, the output file is named untitled.mcs. I would like to configure the project to use an output filename more appropriate to the project I am synthesizing.
I have examined all the properties easily…
Nigel Davies
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1 answer
Syntax error while running the code
The error is in the lines 431,451,452 and 455.
ERROR:- Line 431. Choice .to. is not a static expression.
Line 451. Choice + is not a static expression.
Line 452. Choice + is not a static expression.
Line 455. Choice time_period_counter is not a…
user6514981
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3 answers
Running post-synthesis in Xilinx ISE
How can I run a post-synthesis simulation in Xilinx ISE? I have searched a lot and seen 1 solution on the xilinx website, but wasn't successful in applying it:
https://www.xilinx.com/support/answers/45668.html
Can anybody help me with this?
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1 answer
Syntax error near "Architecture" in vhdl
I'm trying to write a code in xilinx ise 14.7 and vhdl programming language using structural architecture. I have a vhdl module named mux_xor and a top down module named Q1. I get this error in Q1 top down module:
Line 62: Syntax error near…
Pooya Gh
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1 answer
Syntax error near "tmp" in vhdl
I am trying to write a code for serial parallel conversion in Xilinx ise and VHDL language, but I get this error:
Line 57: Syntax error near "tmp".
My VHDL Code is as below:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
ENTITY STP IS
GENERIC(n :…
Pooya Gh
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- 2
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1 answer
how to get power estimation using xpower
I have been working on a class project using Verilog. I had to create a circuit and then calculate the power that the circuit uses. I have been trying to do it using Xpower Analyzer I follow the instruction to create the vcd file, compile and…
Adonis H.
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2 answers
VHDL multiplier which output has the same side of it's inputs
I'm using VHDL for describing a 32 bits multiplier, for a system to be implemented on a Xilinx FPGA, I found on web that the rule of thumb is that if you have inputs of N-bits size, the output must've (2*N)-bits of size. I'm using it for a feedback…
Tebi
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1 answer
Creating a custom pcore for Xilinx ISE 14.7?
A bit of a general question, but what is the most popular/common/easiest way of creating a custom pcore?
I have seen some examples and they were mostly done on Matlab and since I do not have Matlab anywhere, I am a bit lost here. There has got to be…
Joe Carr
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1 answer
Synthesizing full adder with ISE
I wrote a simple full adder which uses 2 half adders and an OR gate. The VHDL code is pretty simple
library ieee;
use ieee.std_logic_1164.all;
entity ha is
port( x: in std_logic;
y: in std_logic;
s: out std_logic;
c: out…
mahmood
- 23,197
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1 answer
FPGA compilation in labview
I have a problem with FPGA compilation. I am using single board rio 9602.
I have installed:
Windows 7 operating system
LabVIEW 2015 sp1 (32bit),
LabVIEW 2015 sp1 FPGA module,
LabVIEW 2015 sp1 Real-Time Module,
NI CompactRIO 16.0- NI CompactRIO…
maua
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- 1
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1 answer
Receving a value from AXI connected to UART
On ISE 14.7, what do I need to do in order to have the AXI stream (which has an ipcore that loops a value) to give me output via the UART?
I had set up the project properly, added a UART and set the mhs, ucf files and the rest of the bonanza,…
Joe Carr
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0 answers
Simple VHDL ALU will not show inputs or overflow in the waveform
I'm supposed to write up a 16-bit ALU. My professor wants us to try and code the adder and sub of the ALU with a
signal tmp : std_logic_vector(16 downto 0); and then in the case for the select input s we put:
tmp <=…
Logan Jordon
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Connecting to FPGA through MATLAB
I am working on a project that requires me to use the system generator option on MATLAB. I connect the Spartan-6 board and generate the Jtag Cosim model. After finishing all of that, I try to run the program and I get an error which states:
Error…
yashz123
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