Specifying the Rise and Fall Time for clocks

Question

I am trying to simulate a D-Flip Flop for Metastability. With ideal clocks generation in Xilinx ISE and Vivado, I cannot see the metastability phenomenon. I need to specify the clock with Rise and Fall time for the metastability to occur. I couldn't find a way to do it in Xilinx. Any suggestions on this are welcome.

score 0 · Answer 1 · answered Jan 16 '17 at 14:48

0

You can provide rise time, fall time & turn off time for any gate delays.

#(1,2,3) not n1 (clk_out, clk_in)

Here

1 - Rise Time
2 - Fall Time
3 - Turnoff Time

answered Jan 16 '17 at 14:48

Karan Shah

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Thanks Karan but how to do it for clocks and other signals? As metastability has a lot to do with clocks. – Swastika Jan 16 '17 at 22:38
I don't understand your point. But this expression can be applied for any logic. – Karan Shah Jan 17 '17 at 02:31
@Swastika you can use `#(1, 2, 3) buf ckBuf (ckOut, ckIn)` between your clock generator and dut input. – Hida Jan 18 '17 at 13:25
@Karan I thought the delays work for logic gates only. – Swastika Jan 24 '17 at 21:51

Specifying the Rise and Fall Time for clocks

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