Synthesizing full adder with ISE

Question

I wrote a simple full adder which uses 2 half adders and an OR gate. The VHDL code is pretty simple

library ieee;
use ieee.std_logic_1164.all;

entity ha is
  port( x: in std_logic;
      y: in std_logic;
      s: out std_logic;
      c: out std_logic);
end;
architecture x of ha is
begin
  s <= x xor y;
  c <= x and y;
end;

and

library ieee;
use ieee.std_logic_1164.all;

entity fa is
  port( a: in std_logic;  b: in std_logic;  cin: in std_logic;
      sum: out std_logic;  cout: out std_logic);
end;
architecture y of fa is
  component ha port( x: in std_logic; y: in std_logic;
                   s: out std_logic; c: out std_logic);
  end component;
  signal im1, im2, im3: std_logic;
begin
  ha1: ha port map( x=>a, y=>b, s=>im1, c=>im2 );
  ha2: ha port map( x=>im1, y=>cin, s=>sum, c=>im3 );
  cout <= im3 or im2;
end;

The output of the synthesizer however shows there are two XOR gates. Where are the OR gate and others for half adder?

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# Xors                                                 : 2
1-bit xor2                                            : 2

=========================================================================

Also, the RTL schematic of the FA is correct, however, the RTL schematic of the half adder is weird! The y port is not present and there is data[1:0]. What does that mean?

FA:

HA:

score 1 · Accepted Answer · answered Mar 24 '17 at 18:08

1

I've seen the Vivado synthesizer leave stuff off of the macro statistics regularly. Macro reports aren't really meaningful for an FPGA design because all your logic is really going to be mapped into LUTs. In this case it looks like your basic and/or gates aren't considered to be macros, but an XOR is (as indicated by it being a box in the schematic instead of a logic symbol).

As far as your half adder schematic, the tools have combined your two single bit input ports into a two bit bus. The triangles before the and gate are taps on that bus to pull one of the two bits out. It's just another way to represent the same thing.

answered Mar 24 '17 at 18:08

QuantumRipple

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The triangles are buffers I think. Still the schematic is weird. The input port x is considered with two signals data[0] and data[1]. I wonder why it didn't put x and y – mahmood Mar 24 '17 at 20:23
No, they're not buffers. I understand that a triangle is frequently used as a schematic symbol for a buffer. In this case they're bus taps. Synthesizers rename stuff all the time; it makes it a pain to read, but apparently produces better results. – QuantumRipple Mar 24 '17 at 20:26

Synthesizing full adder with ISE

1 Answers1