Syntax error near "tmp" in vhdl

Question

I am trying to write a code for serial parallel conversion in Xilinx ise and VHDL language, but I get this error:

Line 57: Syntax error near "tmp".

My VHDL Code is as below:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

ENTITY STP IS
    GENERIC(n : INTEGER :=10);
    PORT(din, clk, s: in std_logic; dout: out std_logic_vector(n-1 downto 0));
END STP;

ARCHITECTURE BEHAV OF STP IS

    Signal tmp : std_logic_vector(n-1 downto 0);
    Signal c : INTEGER := 0;

BEGIN

    PROCESS(s, clk)
    BEGIN
        IF (s'event AND s = '1' AND clk'event AND clk = '1' AND c = n) THEN
            tmp(c) <= din;
            dout <= tmp;
            c <= 0;
        ELSEIF(s'event AND s = '1' AND clk'event AND clk = '1')
            tmp(c) <= din;
            c <= c +1;
        ELSE
        END IF;

    END PROCESS;

END BEHAV;

Can somebody help me to handle this error?

I posted direct answer for your question, but I have to add, that your design is not correct for synthesis. You can only have one statement sensitive on clock edge, and no `ELSE` or `ELSIF` after that statement. — Staszek, May 11 '17 at 11:40
You can already see an error by looking at stackoverflow's syntax highlighting xD — JHBonarius, May 12 '17 at 06:13

Staszek · Accepted Answer · 2017-05-11T13:04:10.897

2

You forgot about THEN in line ELSEIF(s'event AND s = '1' AND clk'event AND clk = '1').

There should also be ELSIF instead of ELSEIF. And actually, in this case there should be no such line, because your process can only have one statement sensitive on clock edge.

edited May 11 '17 at 13:04

answered May 11 '17 at 11:35

Staszek

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now i get this error: Line 55: Syntax error near "THEN" – Pooya Gh May 11 '17 at 11:44
How exactly look this line now? Please, accept edits, or edit your code, so that it looks properly, and add this edited line below your question. – Staszek May 11 '17 at 11:45
now its my code after edit: ELSEIF(s'event AND s = '1' AND clk'event AND clk = '1') THEN Should i use ELSEIF or ELSE IF? – Pooya Gh May 11 '17 at 11:48
You actually shouldn't use any of it. Look at my comment below your question. In other case there should probably be `elsif`. – Staszek May 11 '17 at 12:06

Syntax error near "tmp" in vhdl

1 Answers1