I have been working on a class project using Verilog. I had to create a circuit and then calculate the power that the circuit uses. I have been trying to do it using Xpower Analyzer I follow the instruction to create the vcd file, compile and synthesize the code using Xilinx ISE 14.7 . Everything goes well until the result shows up. I received 0 power consumption from the clock. I try to constrains the clock and it only give me a increment in dynamic power from 0 to 0.009, but not luck in the clock. Also, I try Xpower in my personal computer and at my university computer lab, so I don't think that it is a software bug. Moreover, I have try different design such as a simple alu, register etc. Nonetheless, I still getting the same power result.
More information:
- Testbench runs well and does what I want
- I declare clock like: module toptrafficlight( clock,rst,output );
- List item: I have constrained the clock to 20ns
- Timing phase = 0. After synthesis (not sure what this means)
- Warrnings from:
- HDLCompiler:413 - Line 86: Result of 5-bit expression is truncated to fit in 4-bit target.
- PhysDesignRules:372 - Gated clock. Clock net main_gated_clk is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
Power result from Xpower Analyzer
My questions are?
- is it a way to setup the clock? which I think might be the cause of the problem
- is there anything else needed to be done beside getting the VCD file and synthesize the code?
- any other ideas, examples or tutorial?
