Stack Overflow
Stack Overflow

Questions tagged [xilinx-ise]

Xilinx ISE is the toolchain package for programming Xilinx FPGAs in VHDL and Verilog.

291 questions
0
votes
1 answer

How to move the numerical calculation part from VHDL code to C can run it on NEXY3 Spartan 6 board

I am currently working on a project which requires to use a embedded soft core. I wrote a pong game using VHDL (ISE) and synthesised it onto the FPGA, the next step is going to shift the numerical calculation part to soft core which means i need to…
Harvey Wang
  • 5
  • 1
0
votes
1 answer

VHDL Target Size

I have problem with assignment and cant solve it. In this part of code: KS1 <= regA when Y(5)='0' else not regA(0) & not regA(0) & regA(1 to 3) & "000" when (Y(5)='1' and regA(0)='1') else (not(regA(0) & regA)…
Destroyer
  • 1
  • 1
0
votes
3 answers

Implementing open collector and 'z' data type

I want to implement open collector protocol. When I try to set inout type port to 'Z' value, which is pulled up, it just continue to hold its previous value. To elucidate, I have just written the following VHDL code which first set o_sample_trig to…
Reflection
  • 399
  • 2
  • 11
0
votes
1 answer

Synopsys Synplify Pro synthesis failed when using "``"

When I try to use construction like this my synthesis was failed `define defLOMIC 0 //For example `define rd(LOMIC) `def``LOMIC Late: wire lod = `rd(LOMIC); Error: E CS231 Unknown macro def VDF_TOP.v (368) syntax.log (13) 09:14:32 Thu Dec 06…
Vlad
  • 17
  • 5
0
votes
1 answer

Mapping PCIe BAR regions of size greater than 4MB in Xilinx Vivado

We are developing a system with a custom processor, Microblaze and some peripherals in VC709 FPGA using Xilinx Vivado. We are using two 'PCIe : BARs' in 'AXI Bridge for PCI express gen 3'. The changes we make in the block configuration of the PCI…
vineeshvs
  • 479
  • 7
  • 32
0
votes
1 answer

How to access Verilog genvar generated instances and their signals

I need to initialize arrays in generated instances via generate block in Verilog. I'm trying to use the syntax below, however, I get an error as External reference foo[0].bar.array[0] remains unresolved. in Xilinx ISE. integer i, j; …
yildizabdullah
  • 1,895
  • 5
  • 24
  • 37
0
votes
1 answer

mapping error in verilog

I'm constantly getting this error in my mapping process in Xilinx 8bit processor verilog code: " The design is too large to fit the device." and "ERROR:Pack:2309 - Too many bonded comps of type "IOB" found to fit this device." I have Xilinx…
Mary
  • 81
  • 1
  • 2
  • 11
0
votes
1 answer

Assigning chunk of data from an ipcore output to next ipcore input

I have a set of 16 data stored in BRAM ipcore. Now I have to fetch first 4 at a time and give it to the next IPcore (say FFT) for further processing. Once done with this, I have to feed the next set of 4 data. Is the situation handled by state…
Researchimage
  • 1
  • 2
0
votes
1 answer

Latch generation warning in Verilog 8-bit processor code

I have encountered this warning while synthesizing my 8-bit MIPS processor Verilog code in Xilinx ISE. Xst:737 - Found 1-bit latch for signal <6>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of…
Mary
  • 81
  • 1
  • 2
  • 11
0
votes
0 answers

Random issues on Xilinx Spartan 6

I've been having the same problem for months now. I have a quite heavy FPGA design (60% LUTs on a spartan 6) and every time I want to add a feature, it breaks all the existing features. For instance, one of my main feature is a decoding block which…
A. Kieffer
  • 372
  • 2
  • 13
0
votes
1 answer

TX buffer of Multi-gigabit transceiver GTP

Now I am making a project relating to MGT (Multi-Gigabit Transceiver) GTP. Because I am a newbie in verilog programming language, I have one question about the MGT GTP. In the Xilinx document (Virtex-5 FPGA ROCKETIO GTP transceiver), TX sides…
Tai Chau
  • 33
  • 1
  • 9
0
votes
0 answers

PS2 Keyboard interface runs smoothly in Active-HDL simulator, but not working on Nexys2 Board

I have to make a PS2 Keyboard Controller project at the university and i encountered a few problems when trying to test the system on the FPGA board. It had worked perfectly in the simulator of Active-HDL, but i am not sure what it might be that…
motiondev
  • 41
  • 5
0
votes
1 answer

Shifting transmit data to position of receive data in loopback mode

Now, I am making the protocol (Aurora-Xilinx) to connects two boards together. and I would like to check bit errors for transmit data and receive data. To check bit errors, transmit data on board 1 is looped back on board 2 and then come back board…
Tai Chau
  • 33
  • 1
  • 9
0
votes
0 answers

HDLCompiler:1731 - WASHING MACHINE CONTROLLER VHDL

I am trying to write VHDL language for a washing machine controller, but cannot understand the reason why I am having the errors when I synthesis below: ERROR:HDLCompiler:1731 - Line 152: found '0' definitions of operator "/", cannot determine exact…
Matty Brindle
  • 1
  • 3
0
votes
0 answers

to_string() alternative for VHDL 2002

I need a function that will convert a signal (number) to string, in order to be able to display it on LCD. Unfortunately, I have to use Xilinx ISE 14.7 because Spartan 6 is not supported in Vivado, which does not support VHDL 2008. Is there any…
Marko Gulin
  • 509
  • 3
  • 6
  • 19
1 2 3
…
19 20