Questions tagged [uvm]

Universal Verification Methodology: SystemVerilog class library

From Wikipedia:
The Universal Verification Methodology (UVM) is a standardized methodology for verifying integrated circuit designs. UVM is derived mainly from the OVM (Open Verification Methodology) which was, to a large part, based on the eRM (eReuse Methodology) for the eVerification Language developed by Verisity Design in 2001. The UVM class library brings much automation to the SystemVerilog language such as sequences and data automation features (packing, copy, compare) etc., and unlike the previous methodologies developed independently by the simulator vendors, is an Accellera standard with support from multiple vendors: Aldec, Cadence, Mentor, and Synopsys.

Related Resources

UVM User's Guide 1.1
UVM User's Guide 1.2
IEEE Std 1800.2-2017 (Universal Verification Methodology Language Reference Manual)

527 questions

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1 answer

Accessing internal modules(tb.dut.a.b) apb interface at top tb level

Is there any way I can connect an apb master vip to internal module inside dut which have apb signals in it . I want to program some registers in this deep inside dut module . I tried to connect an interface and bind it at deep inside module ,…

verilog system system-verilog uvm system-verilog-dpi

asked Jul 27 '19 at 15:36

Verifexplorer

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1 answer

Simulation never ends

I'm trying to learn UVM in SystemVerilog. I understand the very ideology of UVM, but I have difficulty writing a working case. I'm trying to write an apb testbench. It compiles and runs, which is already a victory for me, but the transactions…

system-verilog uvm

asked May 08 '19 at 09:48

Андрей Солодовников

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votes

1 answer

UVM indexing into array by get_type_name

Is this possible? Get_type_name is a string. Can't I have an int array and use the name to index in? I get index expression type of illegal. Obj n1; int number[100]; n1 = new(); number[n1.get_type_name] = 1;

verilog system-verilog uvm

asked Apr 19 '19 at 20:27

newton44

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votes

1 answer

Can anyone explain briefly on what does 'ovm_do_with actually does?

I'm new to OVM and Saola. Can anyone explain what does 'ovm_do_with(a,{b=0}) actually does?

sequence uvm

asked Dec 24 '18 at 07:01

Nur Sakinah Burhanuddin

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votes

1 answer

Qualifying SVA's ##[0:$] in a simulation

I have the following SVA property: $rose(hresetn) |-> ( ##[0:$] $rose(signal_a) ##[0:2] ($rose(signal_b)); During a simulation if signal_a never rose (which is functionally acceptable), will my test finish with an error ? Do…

system-verilog uvm system-verilog-assertions

asked Nov 22 '18 at 15:39

El_Gahaf

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1 answer

Accessing a shared memory

I am trying to verify a sMEM design using assertions in systemVerilog however I got a problem I did not Know How to solve it : I am supposed to verify if: On rising edge of CLKA, when BLKA is 1 and RWA is 1, data is read at ADDRA address of…

system-verilog uvm system-verilog-assertions system-verilog-dpi

asked Sep 28 '18 at 08:55

mariam

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votes

1 answer

Unable to locate key in config db using wildchar?

I am not clear on why my lookup in config_db is returning null? My understanding is that config_db allows metacharacter "*" to match zero or more characters for the key. So not sure why it is failing. Below is the trace from +UVM_CONFIG_DB_TRACE.…

uvm

asked Sep 19 '18 at 11:38

Sanjeev Singh

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1 answer

How can I use 'initial begin in the uvm?

I'm trying to implement some systemverilog code within the UVM code. but I come across one syntax error when I comple the uvm code as the below. @test.sv initial begin #100 $finish; end Error-[se] Syntax error Following verilog…

uvm

asked Sep 10 '18 at 04:53

IamUser

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votes

1 answer

what is the purpose of UVM automation macro?

I'm trying to understand about UVM automation macro. among other things, i found some sentence "UVM system Verilog call library also includes macros that automatically implement the print, copy, clone, compare, pack and unpack methods and more" from…

uvm

asked Sep 04 '18 at 03:44

greeting

-1

votes

1 answer

Is there any tools or EDA for easily using systemverilog?

When I use systemverilog, I can not find a good IDE to show the methods of a specific object since systemverlog is a kind of OOP. So I want to know is there any easy to use IDE or tool for systemverlog code and that can also build a testbench?

system-verilog uvm

asked May 31 '18 at 07:56

Songsong Sun

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1 answer

what does `uvm_send signify

what does `uvm_send(seq) do? I am seeing these often in my code. seq is a uvm_sequence which is being randomized and processed arithmetically. Where does `uvm_send(seq) send the sequence?

system-verilog uvm

asked Feb 06 '18 at 15:00

Arvind R

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votes

1 answer

parameterized class queue in sv

In my testbench there are a couple of pcie_agents which have the different lanes. I extended my own class from the pcie VIP. Something like : class mt_pcie_agent#(int INST=0) extends pcie_agent((INTS==0)?2:(INTST==1)?4:(INST==2)?8:16);//different…

system-verilog uvm

asked Sep 04 '17 at 10:04

hyperion007

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votes

1 answer

Why use layered testbench instead of simple one program block?

What is basic purpose of a layered testbench for verification when we can write all functionality in simple one program block. I know reusability is one purpose but what apart from it makes unique.

verilog system-verilog verification uvm

asked Jun 05 '17 at 20:29

Xeroxpop

-1

votes

1 answer

The different between factory, config_dg, and resources_db

I found it sometimes confuse. I will appreciate if someone could clarify the different between factory, config_dg, and resources_db

uvm

asked Oct 09 '16 at 08:21

sara8d

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votes

2 answers

can we do functional verification using JasperGold?

can anybody tell me how to do functional verification using JasperGold?. I am new to this tool.

system-verilog uvm

asked Sep 27 '16 at 09:38

Tsr

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