Questions tagged [uvm]

Universal Verification Methodology: SystemVerilog class library

From Wikipedia:
The Universal Verification Methodology (UVM) is a standardized methodology for verifying integrated circuit designs. UVM is derived mainly from the OVM (Open Verification Methodology) which was, to a large part, based on the eRM (eReuse Methodology) for the eVerification Language developed by Verisity Design in 2001. The UVM class library brings much automation to the SystemVerilog language such as sequences and data automation features (packing, copy, compare) etc., and unlike the previous methodologies developed independently by the simulator vendors, is an Accellera standard with support from multiple vendors: Aldec, Cadence, Mentor, and Synopsys.

Related Resources

UVM User's Guide 1.1
UVM User's Guide 1.2
IEEE Std 1800.2-2017 (Universal Verification Methodology Language Reference Manual)

527 questions

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UVM task based phases - do the components must be sync'ed?

task based phases - do the components must be sync'ed? meaning, can componentA be in reset_phase and componentB be in main_phase? When using objections, that cannot be, right? The objections must be dropped before moving to the next phase. But when…

system-verilog uvm

asked Jan 26 '22 at 09:26

NimrodB

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1 answer

SV assertion to flag incorrect verilog event region

Is there a system verilog construct which can flag an error if a signal toggled in NBA region in verilog event queue? Something like if($toggled_in_nba(clk)) begin `uvm_error() end

system-verilog uvm eventqueue

asked May 21 '21 at 00:52

Jean

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What's the difference between uvm_sqr_if_base::peek() and uvm_sqr_if_base::get_next_item()?

In System Verilog UVM, the interface present in TLM ports for communication between sequences and drivers (uvm_sqr_if_base) offers flexibility. For pulling requests, I'll summarize the four options in this table: blocking …

system-verilog uvm

asked May 06 '21 at 02:05

Lance E.T. Compte

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1 answer

Two Modports of same Interface have 1 clock cycle difference

I'm writing some test environment for practise but facing some strange issue. I have interface and made 2 modports for master and slave. But when I check the waveforms I see that when I change something in using master modports it takes additional…

system-verilog verification uvm

asked Mar 16 '21 at 20:39

Stepan Harutyunyan

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2 answers

Virtual method 'write' not implemented in class

Hello I am getting the above error for the subscriber class I created as following: The error seems in the write function of the class but I am not sure what I am missing in the function. `uvm_analysis_imp_decl(_bfm2dut_change) class…

verilog monitor uvm subscriber edaplayground

asked Mar 12 '21 at 05:55

Ishan Kumar

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1 answer

Using assign inside $test$plusargs in systemverilog

In my code, I want to do some connections using assign statement for all my tests except one test for which I added a runtime argument "HB_CONN_DISABLE" in my testlist. When I code as follows,I get the below error if…

verilog system-verilog uvm

asked Jul 11 '20 at 08:34

Grace90

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1 answer

How do I access methods from sequencer in sequence using p_sequencer?

class fifo_write_sequence extends uvm_sequence#(fifo_seq_item); `uvm_object_utils(fifo_write_sequence) `uvm_declare_p_sequencer(fifo_write_sequence) function new(string name="fifo_write_sequence"); super.new(name); endfunction …

uvm

asked Jul 05 '20 at 16:10

mikasa

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1 answer

What is the difference between uvm_component parent = null, uvm_component parent and uvm_component parent = " "?

What is the difference between uvm_component parent = null , uvm_component parent and uvm_component parent = " " in the constructor function new(string name = " ", uvm_component ) in a given class? Can you also provide some examples for…

system-verilog uvm

asked Mar 10 '20 at 23:34

Rohan Somanchi

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1 answer

uvm configure_phase is never called

Hi I have a testbench environment where I have to do something every test in configuration phase. So I have decided to put in base_test as follows class base_test extends uvm_test; .... task configure_phase(uvm_phase phase); …

system-verilog uvm

asked Feb 29 '20 at 23:27

user1978273

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votes

1 answer

Exclude some design unit from code coverage on Questasim

I run a code coverage on questasim and I got ucdb file as output. But I need to exclude code coverages of some modules that connect to the top module.I don't need some of modules to be covered which this I can improve coverage report. How can I do…

modelsim uvm questasim

asked Jan 14 '20 at 07:50

Buğra Tufan

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1 answer

Questasim - Is it possible to log and reload signals on new design?

I am running a test (UVM) with lot of components. It is a Top-Level test, however I am debugging an internal module and I am only interested in the signals of the interfaces connected to that module. Since it is a TL it takes long time since I get…

verilog system-verilog uvm questasim

asked Nov 07 '19 at 10:45

Hellzzar

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votes

1 answer

capture $finish in uvm_component

I want to capture $finish in uvm_component. I mean my uvm_component needs to execute some custom code when $finish is called. I had used pre_abort call back in uvm_component. But problem is my testbench has multiple uvm_components and they also…

system-verilog uvm

asked Sep 25 '19 at 12:03

Murali Krishna

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1 answer

Both active and reactive UVM agent

I'm developing a UVM agent for a protocol which has both rx and tx transactions on same signals. How do I implement this? I thought about a driver which will get items from 2 different sequencers, one for RX (reactive) and second for TX…

system-verilog uvm

asked Sep 22 '19 at 12:42

VerificationEng

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votes

1 answer

Can a constraint of randomization be in child class while it has been declared in base class. If yes how?

class AAA; rand int a; rand bit b; constraint aaa; class BBB extends AAA ; constraint aaa {a>4 && a<67 ; b>10 && b<90 ;} endclass endclass module mode; AAA p; AAA::BBB q; initial begin p=new; q=new; …

system-verilog uvm

asked Sep 19 '19 at 08:07

Pradyumna Panda

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votes

1 answer

forcing internal DUT signal from UVM driver

I have a scenario. I have uvm_driver which has a virtual interface vif. This virtual interface has modports with signal a. There are two levels of simulation. lower level L1 and upper level L2. In L1, the agent is active and driver drives the signal…

system-verilog uvm

asked Sep 07 '19 at 01:25

user1978273

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