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I'm trying to implement some systemverilog code within the UVM code.

but I come across one syntax error when I comple the uvm code as the below.

@test.sv
    initial begin
        #100 $finish;
    end

Error-[se] Syntax error

Following verilog sourve has syntax error :

"test.sv", 70 : token is 'inital"

inital begin

Can't use initial begin syntex at the uvm?

Thomas
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IamUser
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1 Answers1

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Assuming that your test.sv file is a class, initial blocks are not permitted in classes for SystemVerilog. This isn't a UVM restriction, but a SystemVerilog one.

Brian
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