Universal Verification Methodology: SystemVerilog class library
Class library for system-verilog.
From Wikipedia:
The Universal Verification Methodology (UVM) is a standardized methodology for verifying integrated circuit designs. UVM is derived mainly from the OVM (Open Verification Methodology) which was, to a large part, based on the eRM (eReuse Methodology) for the eVerification Language developed by Verisity Design in 2001. The UVM class library brings much automation to the SystemVerilog language such as sequences and data automation features (packing, copy, compare) etc., and unlike the previous methodologies developed independently by the simulator vendors, is an Accellera standard with support from multiple vendors: Aldec, Cadence, Mentor, and Synopsys.
Related Resources
- UVM User's Guide 1.1
- UVM User's Guide 1.2
- IEEE Std 1800.2-2017 (Universal Verification Methodology Language Reference Manual)
