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I am trying to verify a sMEM design using assertions in systemVerilog however I got a problem I did not Know How to solve it : I am supposed to verify if:

On rising edge of CLKA, when BLKA is 1 and RWA is 1, data is read at ADDRA address of the RAM and the result is available at DOUTA.

in my design the RAM is defined as shared variable

so how can I write assertions ?

mariam
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1 Answers1

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An assertion is not something I would use to verify a memory. Assertions are best for verifying protocols, not functionality. And since your memory is likely a vendor macro, theres no need for you to test its internal functionality. You mainly need to test the connectivity to the memory. There are pre-defined tests that involve writes followed by reads for memory verification.

dave_59
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  • Sorry Mr Dave I did a mistake First my mem is defined as a shared variable not generic what I want to know is weather I can reach a variable using assertions or not thank you – mariam Oct 01 '18 at 11:37
  • Assertions can access any static variable. What do you mean by "shared variable"? That is not SystemVerilog terminology. – dave_59 Oct 01 '18 at 15:07
  • my design is written with VHDL what I meant by shared variable is that MEM can be accessed by many module 'sMEM' 'dMEM' 'ENPMEM' – mariam Oct 02 '18 at 05:46