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I have the following SVA property:

$rose(hresetn) |-> (
        ##[0:$] $rose(signal_a)
        ##[0:2] ($rose(signal_b));

During a simulation if signal_a never rose (which is functionally acceptable), will my test finish with an error ? Do simulators qualify ##[0:$] as an error/violation if it never happened during run-time, or it will be treated as a property never satisfied ?

Thanks.

El_Gahaf
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1 Answers1

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SystemVerilog has both weak and strong properties. By default, everything is weak meaning no match is just an incomplete assertion the neither passes or fails. Some tools can report any assertion attempt that has never completed. But there is also a strong property qualifier that will report an error if there is no match to a sequence by the end of simulation. (Note not all tools have implemented this feature)

dave_59
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