Questions tagged [uvm]

Universal Verification Methodology: SystemVerilog class library

From Wikipedia:
The Universal Verification Methodology (UVM) is a standardized methodology for verifying integrated circuit designs. UVM is derived mainly from the OVM (Open Verification Methodology) which was, to a large part, based on the eRM (eReuse Methodology) for the eVerification Language developed by Verisity Design in 2001. The UVM class library brings much automation to the SystemVerilog language such as sequences and data automation features (packing, copy, compare) etc., and unlike the previous methodologies developed independently by the simulator vendors, is an Accellera standard with support from multiple vendors: Aldec, Cadence, Mentor, and Synopsys.

Related Resources

UVM User's Guide 1.1
UVM User's Guide 1.2
IEEE Std 1800.2-2017 (Universal Verification Methodology Language Reference Manual)

527 questions

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2 answers

Ruby and SystemVerilog DPI

The DPI functionality in System Verilog always mentions that you can interface it with any language, the most common one being C/C++. I want to interface my system Verilog code with Ruby. Is there any documentation or support for this functionality?…

asked Jul 18 '14 at 15:01

noobuntu

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2 answers

UVM testbench - What is the "UVM" way to connect two different drivers to same interface?

In my Testbench, I have an interface that I need to drive. The interface can be driven in 2 different modes, with each mode having its own driver protocol and transaction type. So far, I have designed both uvm_agents separately. Now, I need a way to…

system-verilog uvm

asked May 27 '14 at 20:13

noobuntu

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2 answers

What is the standard methodology of verifying HW when there are cases where RTL and Goldenmodel might produce different but correct output?

I've a UVM test bench (constrained random verification) for my hardware model. My golden model is written in systemC and c++. I have cases where my hardware result won't match with software result but both of them can be potentially correct. As an…

verilog system-verilog uvm

asked May 21 '14 at 00:11

newbie

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1 answer

Handling protocol extensions in a UVC

I'm curious how you handle extensions to a protocol UVC. Let's say we have an APB UVC that implements the AMBA protocol. Let's also say that we have a DUT that, aside from the signals defined in the specification, also implements a few other signals…

system-verilog uvm

asked Apr 28 '14 at 14:16

Tudor Timi

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3 answers

How to check whether a UVM analysis port is connected?

Oftentimes our UVM simulations fail with signatures that we end up debugging to unconnected analysis ports. Is there a way to check up front whether the analysis ports are connected before the run_phase?

system-verilog uvm

asked Jan 30 '14 at 16:51

Victor Lyuboslavsky

9,882
25
87
134

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2 answers

Parameterized class and polymorphism

I was wondering whether there is a better more direct way to make use of polymorphism for a set of classes generated from a parameterized class. The following system verilog code works. Is there a more elegant way ? EDIT: Can I implement something…

class oop polymorphism system-verilog uvm

asked Mar 05 '13 at 16:39

Jean

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119

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4 answers

Race condition with nonblocking assignment in UVM driver

I'm trying to execute for a synchronous driver, I aligned the driven signals to the clock edge as the below. I used nonblocking assignment to avoid race conditions in the UVM driver. When I ran the driver, I got this printed out: myCmd.start:…

system-verilog uvm

asked May 12 '23 at 15:15

bu-ral

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2 answers

is it possible to override uvm test that is specified via +UVM_TESTNAME=test1 by also having +uvm_set_type_override=test1,test2?

I am wondering if it is possible to override test specified in command line via +UVM_TESTNAME by +uvm_set_type_override. I have tried it and this is what i see in prints in log. UVM_INFO @ 0: reporter [RNTST] Running test Test1... UVM_INFO @ 0:…

system-verilog uvm

asked Feb 11 '19 at 16:43

Gautam

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1 answer

Output open array as a formal argument in DPI-C

I have C code (predictor model) that can generate an array of variable length as its result. It is unknown before calling the C code what the size of this array is, and there is some amount of randomization involved (noise modelling) I need to call…

c system-verilog uvm system-verilog-dpi

asked Dec 22 '17 at 18:20

noobuntu

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3 answers

how to use assertoff from test to disable assertion in side uvm object

I am looking for way to disable assert in side uvm component for certain test. Below simple code represent my env, with comment for requirement. I thought I can use $assertoff. I can modify uvm component if required additional instrumentation to…

system-verilog uvm system-verilog-assertions

asked Dec 21 '17 at 19:06

albert waissman

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2 answers

using regex in searching for a field using get_field_by_name

I am trying to get a uvm register field by name in systemverilog. I want to use regex, so that I can use a pattern for the field name. Here is my register fields: YY_XXX_2_N ZZ_BBB_3_N UU_AAA_8_N MM_CCC_4_N YY_WWW_9_N as you can see all register…

regex system-verilog uvm

asked Oct 03 '16 at 17:08

mohammad baba

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3 answers

Why uvm_transaction class when we always extend from uvm_sequence_item?

I was going through basics of UVM tutorials. Everywhere I read the transaction objects are always extended from uvm_sequence_item and not uvm_transaction since uvm_sequence_item has additional features like transaction id, etc. If that is the case,…

system-verilog uvm

asked Jul 08 '16 at 23:29

user1978273

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1 answer

Disable UVM warning TPRGED at time 0

I'm looking for ideas of how to disable a uvm_warning that occurs in the `uvm_object_utils macro. UVM_WARNING @0: reporter [TPRGED] Type name 'xxx_packet' already registered with factory. No string-based lookup support for multiple types with the…

system-verilog uvm

asked Mar 08 '16 at 03:38

Ashley Winn

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2 answers

How do I convert strings to enums in SystemVerilog?

I have command-line plusargs that I want to map to enumerated values. vsim foo +MY_PLUSARG=BAR How do I get the string "BAR" to become the enum BAR?

system-verilog uvm

asked Feb 04 '16 at 22:33

Ray Salemi

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1 answer

Driving two different sequence items in one interface

Let say I have only one interface and multiple definitions of sequence items: class link_pkt extends uvm_sequence_item; class phy_pkt extends uvm_sequence_item; During the test, these items can dynamically be transmitted out through that one…

system-verilog uvm

asked Feb 10 '15 at 07:24

AldoT

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