Questions tagged [uvm]

Universal Verification Methodology: SystemVerilog class library

From Wikipedia:
The Universal Verification Methodology (UVM) is a standardized methodology for verifying integrated circuit designs. UVM is derived mainly from the OVM (Open Verification Methodology) which was, to a large part, based on the eRM (eReuse Methodology) for the eVerification Language developed by Verisity Design in 2001. The UVM class library brings much automation to the SystemVerilog language such as sequences and data automation features (packing, copy, compare) etc., and unlike the previous methodologies developed independently by the simulator vendors, is an Accellera standard with support from multiple vendors: Aldec, Cadence, Mentor, and Synopsys.

Related Resources

UVM User's Guide 1.1
UVM User's Guide 1.2
IEEE Std 1800.2-2017 (Universal Verification Methodology Language Reference Manual)

527 questions

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2 answers

UVM virtual sequencer: choose the right child sequencer

I have a question about virtual sequencer in UVM. Let's think that I have N equal interfaces driven by N equal drivers, each one connected to its own sequencer. What I want to do is to have a transaction like: class my_transaction extends…

system-verilog uvm

asked Nov 12 '14 at 18:19

arandomuser

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1 answer

Specman UVM: What is the difference between access a register directly and using read_reg_val()?

I'm working with vr_ad package for e. I've defined a register my_reg in the vr_ad_reg_file my_reg_file: reg_def MY_REG MY_REG_FILE 20'h00018 { reg_fld my_reg_field : uint (bits : 32) : RW : 0x0; }; I would like to access the value of the…

specman uvm e

asked Oct 30 '14 at 08:36

Halona

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2 answers

Specman e: Is there a way to extend multiple kinds of a struct?

in my verification environment we work with vr_ad UVM package, where there is a general struct for a register vr_ad_reg which has been extended with different type for every register in the environment, etc: reg_def TIMER_LOAD_0 TIMER 20'h00010 { …

specman uvm e

asked Sep 17 '14 at 11:33

Halona

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26

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1 answer

UVM : How to connect multi dimensional arrays in virtual interface?

I have 5 SRAM instances (== 5 different 2-D arrays) in DUT (all in verilog). I want to do backdoor loading on these arrays from a UVM testbench. There are multiple drivers on SRAM array, either from DUT itself or from testbench (from testbench it is…

arrays verilog system-verilog uvm

asked Jul 21 '14 at 13:26

neha

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3 answers

How do you define backdoor access for fields which span two registers?

I have a register map which has 16 bit wide registers. I have a field with is greater than 16 bits wide, so it must span two addresses. How do I define the backdoor access to this field? This is what I tried for my field…

system-verilog uvm

asked Jun 13 '14 at 18:49

nguthrie

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1 answer

How can we add functional coverage while running simulation using NCSIM

I am trying to run a coverage regression using the NC tool from Cadence. I can see RTL coverage, but functional coverage in the scoreboard is missing. How can I add this scoreboard to the covdut option in NCSIM arguments? The scoreboard contains…

system-verilog uvm cadence

asked Feb 18 '14 at 19:54

silentNinJa

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1 answer

Can I derive a register name (available in regmodel) from string

I've a simple sequence regmodel.REGx.write (...) Lets consider I've 8 registers under regmodel viz. REG0, REG1, REG2,....,REG7 I would like to pass number as a test plus argument, say +NUM=4 Using $sformat or $psprintf, I can create string…

system-verilog uvm

asked Jan 27 '14 at 23:31

wisemonkey

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1 answer

How to intercept uvm_error and cause a callback?

I have a UVM scoreboard that has multiple checks that cause `uvm_error. I would like to automatically intercept the uvm_error and dump the contents of my scoreboard. Other engineers will be adding checks to the scoreboard (and its children), so the…

system-verilog uvm

asked Dec 10 '13 at 17:21

Victor Lyuboslavsky

9,882
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134

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1 answer

UVM: illegal combination of driver and procedural assignment warning

I have a UVM testbench for a small block in my chip. In this there is an agent with a driver that drives data on a virtual interface which looks something like this: interface my_if (input bit clk); logic [3:0] opcode; // Clocking block for…

system-verilog uvm

asked Oct 08 '13 at 14:03

nguthrie

2,615
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26
43

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1 answer

What is the meaning of numbers in UVM_INFO?

The following message is from a transcript file created by running QuestaSim to simulate dut. What does the number 39 mean? UVM_INFO /home/Icer/nocc/noc-router/vips/hermes_pkg/src/hermes_agent.sv(39) @ 0: uvm_test_top.env.agent_master_0…

system-verilog logfile uvm questasim

asked Jul 23 '23 at 08:58

benjstark

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2 answers

UVM basic structure: what is the new function?

I'm a beginner in design verification. I wonder why the code below is used in almost every class. class uvm_test_top extends uvm_test; `uvm_component_utils(uvm_test_top) function new (string name, uvm_component parent); …

verilog system-verilog uvm

asked May 18 '23 at 11:03

Derick

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1 answer

Why does begin/end allow me to declare a variable partway through a SystemVerilog task?

I am trying to execute a sequence within the run_phase() task of a uvm_test derived class. I raise an objection at the start of the task; declare, create, and execute a sequence on a sequencer; drop the objection. task run_phase(uvm_phase phase); …

verilog system-verilog uvm

asked Mar 09 '23 at 14:23

Justin Low

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1 answer

How to handle inter-process communication between TLM FIFOs that may or may not be written to this timestep

I want a UVM component that has two input TLM FIFOs and one output AP. For the two inputs, one receives packets that build state, and the other receives packets for querying the state that was previously built. The output AP broadcasts the state…

system-verilog uvm

asked Oct 03 '22 at 19:37

Sean McLoughlin

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1 answer

UVM End of test Objection Mechanism and Phase Ready to End Implementation

I am exploring different ways to end a UVM test. One method that has come often from studying different blogs from Verification Academy and other sites is to use the Phase Ready to End. I have some questions regarding the implementation of this…

system-verilog uvm

asked Nov 06 '21 at 11:50

abdul rauf

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1 answer

How to get property of class handle after override in UVM?

I'm trying to understand UVM Override. I was made a simple Override example as the below module test_module (); `include "uvm_macros.svh" import uvm_pkg::*; class agent_a extends uvm_agent; `uvm_component_utils(agent_a) function…

system-verilog uvm

asked Sep 17 '21 at 06:22

MoniCa

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