Questions tagged [uvm]

Universal Verification Methodology: SystemVerilog class library

From Wikipedia:
The Universal Verification Methodology (UVM) is a standardized methodology for verifying integrated circuit designs. UVM is derived mainly from the OVM (Open Verification Methodology) which was, to a large part, based on the eRM (eReuse Methodology) for the eVerification Language developed by Verisity Design in 2001. The UVM class library brings much automation to the SystemVerilog language such as sequences and data automation features (packing, copy, compare) etc., and unlike the previous methodologies developed independently by the simulator vendors, is an Accellera standard with support from multiple vendors: Aldec, Cadence, Mentor, and Synopsys.

Related Resources

UVM User's Guide 1.1
UVM User's Guide 1.2
IEEE Std 1800.2-2017 (Universal Verification Methodology Language Reference Manual)

527 questions

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1 answer

Randomization in uvm

It would be great if you could help me in understanding how randomization works in UVM and what factors affect it apart from ntb_random_seed . I am observing a testcase which is using same ntb_random_seed is following different randomization only…

system-verilog uvm

asked Sep 19 '16 at 17:18

learner4

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2 answers

UVM-SystemC example run script not working

I've developed a perl script to run UVM-SystemC example codes. #!/usr/bin/perl use warnings; use strict; sub main(); my $CLIBS = "\$SYSTEMC_HOME/lib-linux64"; my $UVMCLIBS = "\$UVMSYSTEMC_HOME/lib-linux64"; my $CINC =…

perl linker uvm systemc

asked Jul 22 '16 at 18:52

MayurKubavat

-1

votes

1 answer

custom report_server not working

The below code is not working class my_report_server extends uvm_default_report_server; `uvm_object_utils(my_report_server) function new(string name="my_report_server"); super.new(); $display( "Constructing report serevr…

system-verilog uvm

asked Feb 18 '16 at 06:41

Saravanan Shanmugavelu

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votes

1 answer

Significance of 'this' keyword in start method

I'm confused with use of keyword 'this'. Case1: sequence.start(get_sequencer, this); Case2: sequence.start(get_sequencer); Both the cases are compiling without error. But case2 is giving is giving a violation in rules check stage.I want to know…

system-verilog uvm

asked Aug 07 '15 at 13:26

Yaswanth

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votes

1 answer

Using interprocess synchronization in Systemverilog

I need to model some portion of my hardware in systemverilog and it kind of looks like following: I can have two treads -(SV task) running in parallel. Thread: 1. get_resource_from_manager() [sema.get(1) ??] 2. repeat(until_finish) 3. …

verilog system-verilog uvm

asked Jun 16 '14 at 23:04

newbie

4,639
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1 answer

C code works standalone. But when UVM test calls C DPI, c variables gets messed up

I am using Synopsis VCS compiler. My testbench is coded in UVM. I have a set of C routines that perform some standalone functions. I am calling these C routines through DPI imports in the UVM environment. Here is the code snippet in a simple…

c dpi uvm

asked May 21 '14 at 22:14

user3662733

-1

votes

1 answer

Multiple slave agent in UVM

I am planning to implement multiple slave agents in my env and a single master agent. Can anybody show me an example how to use this feature in UVM.And how do we start the item for a particular slave sequencer from the testcase.

system-verilog uvm

asked Mar 28 '14 at 12:04

user3383729

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votes

2 answers

UVM: Does setting values to sequence_item before I call start_item(seq_item) cause any issue?

I am setting values to sequence_item before I call start_item(seq_item) any different from setting values after calling start_item(seq_item)?

verilog verification system-verilog uvm

asked Dec 12 '13 at 17:10

shicky

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14
21

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2 answers

Why uvm_driver class is not abstract class while other like class uvm_sequence also parameterized class but it is abstract one?

Here here different UVM class signatures: virtual class uvm_env extends uvm_component; virtual class uvm_scoreboard extends uvm_component; virtual class uvm_monitor extends uvm_component; class uvm_sequencer #(type REQ=uvm_sequence_item, RSP=REQ) …

system-verilog uvm

asked Aug 04 '23 at 16:28

AnuragChauhan

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votes

2 answers

x.stop_sequences() is causing this UVM FATAL Item_done() called with no outstanding requests

x.stop_sequences() is causing this UVM FATAL Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item() Can someone tell me how to use stop_sequences while making sure the…

uvm

asked Dec 12 '20 at 10:12

uvm123

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1 answer

If I have a fixed size array , how do I write a constraint so that each multi-bit element of the array after randomization is an odd number

I need to generate odd numbers after randomizing elements of an array in UVM sequence .

uvm

asked Jan 14 '19 at 21:03

Grace90

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votes

1 answer

Systemverilog code error: near "" gmii_interface": Syntax error, unexpected IDENTIFIER, expecting class

I see a compile error: // near " gmii_interface": Syntax error, unexpected IDENTIFIER, expecting class"// in Model SIM when i compile the following testcase.sv code: `include "D:/users/rajesh/GMII/interface.sv" `include…

verilog system-verilog uvm

asked Jun 22 '14 at 07:07

AVAV

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votes

1 answer

Null Object Access error in system verilog

I am trying to perform binary tree insertion and in order traversal in System Verilog using OOPs concepts. I am getting error that the object is being used before creating it. Please take a look at the code and help me if someone find any…

class oop system-verilog uvm

asked Jul 26 '21 at 08:17

srij

-3

votes

1 answer

How to eliminate race condition on a variable in systemverilog?

I have a variable in systemverilog that I am setting from a task and reading from another task. The read and the writes are independent. I want to ensure if both read and write are called at the same timestamp I get the updated value. I can see…

verilog system-verilog uvm

asked Dec 05 '19 at 06:08

justrajdeep

-3

votes

2 answers

How to write UVM monitor in SystemVerilog

Could anyone show me an example on how to write the Coverage monitor in Systemverilog as I am new to this. I need to understand the monitor any examples or references is also fine

system-verilog monitor uvm

asked Apr 19 '17 at 10:01

user1802617

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