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Questions tagged [test-bench]

A test bench or testing workbench is an (often virtual) environment used to verify the correctness or soundness of a design or model, for example, that of a software product.

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VHDL write to file does nothing

I wrote an image manipulation piece of VHDL code. For testing, I created a file of pixel values with Matlab and a relatively simple testbench (it just fills the values from file to the input). I wanted to write results to a new file, so that I can…
FlyinGazebo
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verilog program counter syntax error

So I'm getting a syntax error for my program counter test bench and I can not figure out why I keep getting Following verilog source has syntax error: "pc_tb.v", 20: token is 'initial' initial ^ Am i using initial wrong? Making a pipelined…
Nuf
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Test for connectivity between two points in a schematic

I work for a semiconductor manufacturer. We are often trying to test our designs to make sure that sequences we run on our parts properly connect two points on a schematic for example signal_a and signal_b. The two signals usually have multiple pass…
matt
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Realizing Top Level Entity in Testbench using VHDL

I'm a newbie in VHDL and hardware world. I'm trying to make a Count&Compare example using Top Level Hierarchy and test it with testbench and see the results on ISIM. Here is my block diagram sketch: So I end up these 3 vhd source…
unnamed
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Write C statement in VHDL

I am new to VHDL, but I have managed to create a processor in VHDL with some help (it has ALU, multiplier, and a bus architecture to access SRAM memory). The processor decodes 32-bit instructions (which contains the type of operations and the memory…
James the Great
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Verilog Making a divide by two counter out of D Flip Flops not working

I have a working DFF under the module below. d_flip_flop_edge_triggered DFFT(Q, Qn, C, D); However when I switch the "D" input to "Qn" - to make a devide-by-2 counter - the test bench output does not show either Q or Qn. Its red as if there was an…
Serg
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Simulation of Modelsim launching from Quartus doesn't work properly

This is the test bench `timescale 1 ps/ 1 ps module sum_fix_vlg_tst(); reg select; reg [7:-8] valor_a; reg [7:-8] valor_b; // wires wire [8:-8] result_fx; sum_fix i1…
sujeto1
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In SystemVerilog test-benches how do I best describe multi-cycle transactions that can be interleaved

I would like to describe transactions using tasks. I am using a clockingblock cb. This task is kind-of what I want to do, but the value of write seams to be random when doing like this, I guess there is no defined ordering on who gets to drive write…
AxelOmega
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verilog- building a small combinational circuit

I want to build a small combinational circuit(a few or's, 1 and, 1 not gates), and I stumbled upon a problem in the test bench(maybe even before) and was hoping that someone can help me. the circuit is here This is the code: module hewi(input…
bigroman
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How to find the size of a reg in verilog?

I was wondering if there were a way to compute the size of a reg in Verilog. I researched it quite a bit, and found $size(a), but it's only in SystemVerilog, and it won't work in my verilog program. Does anyone know an alternative for this?? I also…
Lynn Bou Nassif
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Delay in VHDL process between adjacent statements

I'm experimenting with VHDL and have come across a delay that I can't get rid of. I'm attempting to program a very simple 3 input AND gate on a testbench that cycles through all the possibly inputs for the AND3 and the subsequent output. I've tied…
davidhood2
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Why doesn't testbench include all signals in calculation?

It is my 1st year in Computer Science Department, and I'm taking a Logic Design course and working in Verilog. This problem appeared. How can I fix it? The assignment says: Implement the Boolean function y=a ⊕ b ⊕ c where ⊕ represents the…
user2971559
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Can anyone help me to create a Verilog testbench?

Can anyone help me create a testbench or just the input code for my following code? I'm using XILINX. module fsmb (input rst,clk,a, output reg x); parameter sta = 2'b00, stb = 2'b01, stc = 2'b10, std = 2'b11; reg[1:0] st,…
Steven Li
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Shift right in vhdl without using srl

I am currently working on implementing a code that performs a right shift on a 23-bit array. However, I am facing some issues: I'm not sure why, but when I visualize the 'din' signal using GTKWAVE, I always find a '0' at the beginning of my input…
Test Prova
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Data bit not incremented during one clock cycle in mod16 counter

I am a beginner in Verilog designing and following is the design and test bench code I wrote for mod16 counter with load. Design.v module counter( input clk, input reset, input load, input [3:0] data); always @(posedge clk) begin …
Dhanashri P
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