verilog- building a small combinational circuit

Question

I want to build a small combinational circuit(a few or's, 1 and, 1 not gates), and I stumbled upon a problem in the test bench(maybe even before) and was hoping that someone can help me.

the circuit is here

This is the code:

module hewi(input D3,D2,D1,D0,output A0,A1,V);

  wire k,s; //outputs of the and and not gates
  not N01(k,D2);
  and An1(s,k,D1);
  or Ou1(A0,D3,s);
  or Ou2(A1,D3,D2);
  or Oufinal(V,D3,D2,D1,D0);
endmodule

This is the test-bench code

module test_benche();

  wire D3,D2,D1,D0,A0,A1,V;
  hewi test(D3,D2,D1,D0,A0,A1,V);

  initial 
  begin
    D3 = 1`b0;
    D2 = 1`b0;
    D1 = 1`b0;
    D0 = 1`b0;
    #50;
    D3=1`b1;
    D2=1`b0;
    D1=1`b1;
    D0=1`b1;
  end
endmodule

The problem I receive is that it can't check any one of these expressions:

Undefined macro exists as: 'b0'   
  "testbench.sv", 8: token is '`b0'
         D3=1`b0;
                ^

What am I missing here?

It looks like you are using backtick ` instead of single quote ' — andrsmllr, Dec 13 '15 at 23:17
I corrected my mistake- the next thing it writes after I compile it again is : **Error-[IBLHS-NT] Illegal behavioral left hand side testbench.sv, 15 Net type cannot be used on the left side of this assignment. The offending expression is : D1 Source info: D1 = 1'b1;** for every one of the expressions i gave values to. — bigroman, Dec 14 '15 at 08:26
Next time please add separate question for follow up questions. That way the best answer for each section can be accepted. — Morgan, Dec 14 '15 at 09:00

score 2 · Answer 1 · answered Dec 14 '15 at 01:02

The syntax error is because you are using backtick (`) instead of single quotes (')

All compiler directives are preceded by the (`) character. This character is called grave accent (ASCII 0x60). It is different from the character ('), which is the apostrophe character (ASCII 0x27). The scope of a compiler directive extends from the point where it is processed, across all files processed in the current compilation unit, to the point where another compiler directive supersedes it or the processing of the compilation unit completes. The semantics of compiler directives is defined in LRM Section 3.12.1 and 5.6.4.

score 1 · Accepted Answer · edited Dec 15 '15 at 00:01

1

Regarding the following error :

Error-[IBLHS-NT] Illegal behavioral left hand side testbench.sv, 15 Net type cannot be used on the left side of this assignment. The offending expression is : D1 Source info: D1 = 1'b1

wires can not be assigned in always or initial blocks. Therefore They need to be converted to reg type.

//Control signals reg type
reg  D3,D2,D1,D0;
//Outputs driven from DUT wires
wire A0,A1,V;
  hewi test(D3,D2,D1,D0,A0,A1,V);

  initial 
  begin
    D3 = 1'b0;
    D2 = 1'b0;
    D1 = 1'b0;
    D0 = 1'b0;
    #50;
    D3=1'b1;
    D2=1'b0;
    D1=1'b1;
    D0=1'b1;
  end
endmodule

edited Dec 15 '15 at 00:01

Greg

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answered Dec 14 '15 at 08:58

Morgan

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Thanks! do you have any idea where I can actually see the test bench at work( meaning interactively how the circuit works)? – bigroman Dec 14 '15 at 09:11
Either use `$display` in the testbench to print to command line, or enable waveform dumping to view in waveform viewer. – Morgan Dec 14 '15 at 09:33
@Greg Thanks for the fix, missed that. – Morgan Dec 15 '15 at 08:20

verilog- building a small combinational circuit

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