I work for a semiconductor manufacturer. We are often trying to test our designs to make sure that sequences we run on our parts properly connect two points on a schematic for example signal_a and signal_b. The two signals usually have multiple pass gates that have to be turned on to connect the two signals. To check that this happens correctly we usually go through the schematic and simulation to check that all the pass gates were turned on correctly. It seems like Verilog would already have a built in command for checking this. For example something similar to:
@triggering_signal
begin
connected=check_connection(signal_a,signal_b)
end
connected would be set to 1 if they are connected and to 0 if they are not. I would appreciate it if anybody could point me in the correct direction if something like this exists. Note I thought of putting a force signal in the code to toggle signal_a and seeing if it shows up at signal_b using a counter, but this does not work for all the cases I need due to the fact that signal_a being at any other state than 1 turns the die off.
