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It is my 1st year in Computer Science Department, and I'm taking a Logic Design course and working in Verilog.

This problem appeared. How can I fix it?

The assignment says:

Implement the Boolean function
y=a ⊕ b ⊕ c
where ⊕ represents the exclusive OR operation.

I wrote this:

module experiment1(A,B,C,F);
input A,B,C;
output F;

reg F;
always@(A or B or C)
    F<= A^B^C;
endmodule

When I run the testbench, it only takes A and B; it does not include C.

Then I add "C" to the testbench, and it works fine. Why doesn't the testbench add "C" into the calculation automatically?

Testbench code:

module tb_experiment1;

// Inputs
reg A;
reg B;

// Outputs
wire F;

// Instantiate the Unit Under Test (UUT)
experiment1 uut (
    .A(A), 
    .B(B),
    .F(F)
);

initial begin
    // Initialize Inputs
    A = 1;
    B = 0;

    // Wait 100 ns for global reset to finish
    #100;
    
    // Add stimulus here

end
endmodule
toolic
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    Verilog tip: Use automatic sensitivity list. `always @*`. For combinatorial code use blocking assignment `F = A^B^C;` – Morgan Oct 12 '14 at 06:04
  • @Morgan actually this doesnt work but i write this and it works: begin F<= A^B^C; end – user2971559 Oct 12 '14 at 19:27

1 Answers1

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You need to connect C to your UUT, and then drive it with a known value:

module tb_experiment1;

// Inputs
reg A;
reg B;
reg C;

// Outputs
wire F;

// Instantiate the Unit Under Test (UUT)
experiment1 uut (
    .A(A), 
    .B(B),
    .C(C),
    .F(F)
);

initial begin
    // Initialize Inputs
    A = 1;
    B = 0;
    C = 1;

    // Wait 100 ns for global reset to finish
    #100;

    // Add stimulus here

end

endmodule
toolic
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