It is my 1st year in Computer Science Department, and I'm taking a Logic Design course and working in Verilog.
This problem appeared. How can I fix it?
The assignment says:
Implement the Boolean function
y=a ⊕ b ⊕ c
where ⊕ represents the exclusive OR operation.
I wrote this:
module experiment1(A,B,C,F);
input A,B,C;
output F;
reg F;
always@(A or B or C)
F<= A^B^C;
endmodule
When I run the testbench, it only takes A
and B
; it does not include C
.
Then I add "C" to the testbench, and it works fine. Why doesn't the testbench add "C" into the calculation automatically?
Testbench code:
module tb_experiment1;
// Inputs
reg A;
reg B;
// Outputs
wire F;
// Instantiate the Unit Under Test (UUT)
experiment1 uut (
.A(A),
.B(B),
.F(F)
);
initial begin
// Initialize Inputs
A = 1;
B = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule