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I have a working DFF under the module below. 

d_flip_flop_edge_triggered DFFT(Q, Qn, C, D);

However when I switch the "D" input to "Qn" - to make a devide-by-2 counter - the test bench output does not show either Q or Qn. Its red as if there was an error.

Here's the full code:

module divBy2UsingDFF(Q, Qn, C, D
    );
   output Q;
   output Qn;
   input  C;
   input  D;
    wire Qn;
    d_flip_flop_edge_triggered DFFT(Q, Qn, C, Qn);

endmodule

I'm new to verilog and I am guessing its a syntax problem.

Morten Zilmer
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Serg
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1 Answers1

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Check the Q value in the simulator, since the red probably means X, which indicates that the data value of the flip-flop is undefined, which is usually the case after reset.

There are several ways to address this:

  • Use a flip-flop with an asynchronous reset
  • Add a synchronous load for the data flip-flop

Btw. instead of instantiating a DFFT you could write the flip-flop divider with an always. Also the wire Qn; is not required.

Morten Zilmer
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  • Yes the Q value is X. I defined the input C in the simulator so I don't know why its showing that. It also has no reset. I think the problem may be that I'm using Qn as both and output and an input? I'm not sure what you mean by writing it with always? – Serg Mar 20 '16 at 20:29
  • No, use of Qn output to feed the input is fine, but the problem is that the internal flip-flop storage is initially undefined, thus has to be defined as either 0 or one after start. Consider yourself; what is the initial value of a flip-flop after power on ? – Morten Zilmer Mar 20 '16 at 20:32
  • The initial value is undefined! Ah I see what you are saying. Is there a way I could initiate the variable from within the code? – Serg Mar 20 '16 at 20:39
  • Suggestions for initialization are use FF with async reset, or load a value initially, as said in the bullets for "There are several ways to address this:". – Morten Zilmer Mar 20 '16 at 21:40
  • Finally got it to work thanks to your suggestions. Thanks – Serg Mar 21 '16 at 03:13