A test bench or testing workbench is an (often virtual) environment used to verify the correctness or soundness of a design or model, for example, that of a software product.
Questions tagged [test-bench]
292 questions
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Why is this line getting the error : Expecting a left parenthesis ( '(' ) [12.1.2][7.1(IEEE)]?
I have a Verilog code for a simple multiplier as shown below, which takes two 32-b inputs which are split into two (16-b MSB and 16-b LSB) and multiplied:
parameter WordLen1 = 32, WordLen2 = 16;
output [WordLen2-1:0] M;
input clk;
input signed…
priscilla
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How can I automatically scale a $display column width?
Disclaimer: I answered my own question, which is explicitly encouraged. I noticed a colleague at work writing code that left the simulation log file difficult to read. I searched the site for a solution, but found none.
I want to $display strings…
toolic
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Functional Coverage for Verilog based TB
I am currently developing a Verilog based Testbench model for a DUT,
I have experience with System Verilog TB and Verification IPs and this is my first time developing a pure verilog TB.
I have completed the basic blocks for running the simulation…
Sreejin TJ
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How can i writing test bench for multiple module?
I am new in this field,
I don't know if they've been asked before.
I'm writing code by creating separate modules to get used to big projects.
I have no problems creating modules, but I don't know how to create a testbench.So I should write test…
Fatma Vural
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1 answer
System Verilog - Reading a line from testbench and splitting the data
I'm a beginner in SystemVerilog Programming. I have a file called "input.in" and it has around 32 bits of data. The value is present in only one line of the file.
The data once sent from the testbench must be split into an array or 4 variables, each…
Shravan Shah
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1 answer
How to test a pipelined module
I'm new to verilog, Is there a difference between writing a test bench for a pipelined module and writing a test bench for an ordinary module?
I just need a simple example clarifying the expected difference in the test bench code for testing a…
Salma El-Sokkary
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Error: (vsim -3389),
I don't understand why I'm getting this error when using model-sim, I've tried a lot of fixes but don't seem to get around this.
This is what my modelsim transcript says:
** Error: (vsim-3389) C:/Users/VRN/Desktop/sha256/t_processing.v(31): Port…
vrndandu
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votes
1 answer
Test Bench code won't work in verilog for pipelined processor
I am designing a simple pipeline processor in verilog. I think my code is fine, but nothing happens when I run my test bench. I instantiate all my variables but my always blocks seem to be being ignored. I have copies of my processor code and test…
BizarroZaalbar
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Verilog Arbiter circuit not producing expected output
I have an arbiter module set up as follows:
// Code your design here
module arbiter#(parameter WIDTH=3)(
input clk,rst,
input [WIDTH-1:0] in,
output reg [WIDTH-1:0] out
);
parameter IDLE=3'b0,G1=3'b001,G2=3'b010,G3=3'b100;
…
Lew Wei Hao
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1 answer
Multiplier 4-bit with verilog using just full adders
I am trying to write the test bench part but I don't know how to do it. Basically, I want to test out 0x10 or 5x5. I don't if what I have is right.
here's a pic to give you some idea of what i am trying to build. it is not this exact one.
Here is…
CharleBarkely123
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Syntax error near "in" of VHDL testbench in ISE14.7
I am writing a testbench to simulate the component top_tb, but it displays a following syntax error.
XX/selfloop_in_chip_tb.vhd" Line 47: Syntax error near "in".
ERROR:ProjectMgmt - 1 error(s) found while parsing design hierarchy.
I have checked the…
tranquil
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votes
1 answer
Drive internal signals in verilog from system verilog testbench
How can you drive internal signals of a DUT verilog code from testbench?
Consider this following example:
module dut(input bit clk);
logic [7:0] data;
endmodule : dut
module top;
bit clk;
dut dut1(.*);
assign dut.data = '0; //…
user3303020
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Problem passing parameters into main function in C++ test bench
I'm trying to test a function I have created in C++ by using a testbench. The main function parameters are two 8x8 arrays:
void multiplyArray2(int A[8][8], int B[8][8]){
In my test bench file, I have created an input array of values and an output…
Harry Reid
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1 answer
SystemVerilog : fork - join and writing parallel testbenches
I am following the testbench example at this link:
http://www.verificationguide.com/p/systemverilog-testbench-example-00.html
I have two questions regarding fork-join statements. The test environment has the following tasks for initiating the test:…
tnugent97
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votes
1 answer
testbench: how to load a known sequence of bits on 1bit data input
-In my Verilog test bench i would like to continuously load a known sequence of bits to the da+ input port (size 1bit) and change following the posedge or negedge edge of clock DCO+.
-This is the sequence that i would like to load on DA+ : 1010…
ahmedcssforever
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