-1

I am a beginner in Verilog designing and following is the design and test bench code I wrote for mod16 counter with load. Design.v

module counter(
  input clk,
  input reset,
  input load,
  input [3:0] data);
  always @(posedge clk)
  begin
    if(reset)
      data<=4'b0000;
    else if(load)
      data<=load_input;
    else
      data<=data+1'b1;
  end
endmodule

Testbench.v

module counter_tb ;
  reg clk;
  reg reset;
  reg load;
  reg[3:0] load_input;
  reg[3:0]data;
  counter ct_1(.*);

  initial begin
   clk = 1'b1;
   load = 1'b0;
   load_input = 4'b0000;
  end
  
  always begin #1 clk=~clk;end
  initial begin
    reset=1'b1;
    #20;
    reset=1'b0;
    #10;
    load=1'b1;
    load_input=4'b0011;
    #10;
    load=1'b0;
    load_input=4'b0000;
  end

  initial begin
    $monitor("time=%0d,reset=%b,data=%d,load=%d,load_input=%d\n",$time,reset,data,load,load_input);
  end
endmodule:counter_tb

The output I obtained with the monitor:

time=29,reset=0,data=5,load=0,load_input=0

time=30,reset=0,data=5,load=1,load_input=3

time=31,reset=0,data=3,load=1,load_input=3 ..

The question is inspite of clock completing one cycle from time=29 to time=30, the data has remained constant = 5 and not incremented by 1 as per the design code.

Everything else is as expected.

What have I missed? Can anyone help me out!

Thanks in advance.

Dhanashri P
  • 111
  • 5

1 Answers1

-1

I agree that initially there were some syntax errors but they all were minute typos while typing the question.

Answering my own question : The logic of my design code was that at every posedge of the clock the data needs to be incremented by 1. At the time=30 the clk=0 which is negative edge and hence the data is not incremented by 1. Hence the data remained constant at time=30 and at time=31 it incremented by 1.

Thanks to everyone who tried to answer my question..

Dhanashri P
  • 111
  • 5