A test bench or testing workbench is an (often virtual) environment used to verify the correctness or soundness of a design or model, for example, that of a software product.
Questions tagged [test-bench]
292 questions
2
votes
2 answers
8 bit comparator from 4 bit comparator - undefined outputs
I have the following code that correctly compares numbers when they are equal to or greater than one another. It does not however generate a less than output. It always pops out as undefined.
What am I missing here?
module FourBitComparator (input…
Anas Yousef
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2
votes
2 answers
Show a fixed point value in vivado
Let's say I have a fixed point value in my VHDL - Code which is defined as std_logic_vector. I know that my last 4-bit are the decimals.
When I use the simulator it will of course not see the last 4 bits as decimals, is there any possibility to…
Kev1n91
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2
votes
1 answer
How can I get internal signals to testbench in VHDL 97 and ISim?
I'm working in a testbench with VHDL 97 and Xilinx ISim, and I'm looking for a way to know the value of a UUT internal signal (like spy function in Modelsim) from code instead of waveform.
I know that I can do easily with VHDL-2008 and alias but…
ferdepe
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2
votes
2 answers
Package procedure calls for testbench stimulus
I have various designs that use an FPGA on a parallel bus with a Microcontroller. For each design I have a testbench were I simulate several Read/write operations on the bus, using procedures that emulates the MCU timing.
I'd like to know a good…
Lasse
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2
votes
1 answer
Vivado 2016.2 Simulator doesn't support System Verilog $cast or $sformatf
Using the Vivado 2016.2 simulator I need to cast an int to a string in System Verilog but $cast and $sformatf are not supported. What other functions or methods are available to me in order to successfully typecast an int to a string?
Bdog
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2
votes
4 answers
In Verilog, I'm trying to use $readmemb to read .txt file but it only loads xxxxx (dont cares) on memory
I need to load a memory with some data originally in binary. I read that $readmemb can be use for this, and there is even a method to make synthesizable.
So, I created another module named RAM_IN (which is not the testbench module) and "connected"…
sujeto1
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2
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1 answer
Specman: Why test has not finished after the MAIN sequence is finished?
a test I've wrote does not finishes after the MAIN sequence is finished.
I did not raise TEST_DONE objection.. and the objections I did raised were all dropped.
Actually the test finished long after all sequence's flow is done, on TEST BENCH…
Halona
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2
votes
1 answer
Verilog testbench
I wanted to write my own testbench, but it doesn't give me an output. Can anyone give me a hand with this?
module direct(clk, reset, x, y);
input clk, reset;
input signed [7:0]x;
output signed [23:0]y;
reg signed [23:0]y;
reg signed [15:0]a[0:8];…
kubauser
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1
vote
1 answer
Testbench of a simple compare-two-values design output is always x
Here is the design that is supposed to compare two floating point numbers:
// IEEE 764: FP[31] = sign, FP[30:23] = exp, FP[22:0] = mantissa
module compare_fp(input [31:0] floatA,
input [31:0] floatB,
output reg…
Zoey
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1
vote
1 answer
Why do I get "object std is not declared" error when I use std::randomize?
I am trying simulate a SystemVerilog code for an N-bit full adder, but I am getting this error:
Error (10161): Verilog HDL error at full_adder_tb.sv(73): object "std"
is not declared. Verify the object name is correct. If the name is
correct,…
KS Hewa
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1
vote
1 answer
Multi-master AXI interface connections
Do we need to have three instantiations of AXI master interface in top file if we have 3 AXI masters and then send these three interfaces to 3 AXI agent instantiations using the config_db? Or, how does it work in case of a multi-master scenario to…
Grace90
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1
vote
1 answer
Testbench: having trouble monitoring register outputs of inner modules
I've been studying Verilog for a short while, and I'm having trouble testing a module I created (it's a 4-bit counter).
Here's my code:
module Counter4bit(input clk,rst,load, input[3:0] parallel_input,
output reg[3:0] o);
always @(posedge clk,…
Amirreza Nadi
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1
vote
1 answer
Generation of up/down counter waveform
I tried to generate a waveform for a 4-bit up/down counter in modelsim; my code got compiled, but it is stuck to zero not getting the values based on the values of up_down.
module up_down_counter(clock, din, load, up_down, resetn, count);
input…
Avadhoot Sagrolikar
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1
vote
1 answer
Code for an adjustable countdown timer that can be set to different countdown values
My code isn't running .
It is Verilog code for an adjustable countdown timer that can be set to different countdown values: 1000 seconds to 0 seconds, 500 seconds to 0 seconds, 60 seconds to 0 seconds, and 9 seconds to 0 seconds.
module…
oli bb
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1
vote
2 answers
Reset a simple counter
I'm trying to write a simple counter using Verilog on Quartus Prime and a testbench in Verilog being tested with Questa FPGA modelSim.
The goal of my counter is to count up to 7 at positive edge of a clock cycle and wrap back to 0 after 7 or if the…
