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Questions tagged [test-bench]

A test bench or testing workbench is an (often virtual) environment used to verify the correctness or soundness of a design or model, for example, that of a software product.

292 questions
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Task does not update testbench sclk

I'm trying to understand why my signal is not updating when it is processed by the task. As you could see below, the problem is related to the signal that internally on the task are changing correctly but even in a hierarchical call do not change…
J. Damone
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How to implement a test bench for 4x1 mux

I'm struggling to write a test bench for this: --------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.all; --------------------------------------- ENTITY mux IS PORT ( a, b, c, d, s0, s1: IN STD_LOGIC; y: OUT…
Ngoloo
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How to resolve design.sv:1 : syntax error on the EDA playground for the sillyfunction taken from Digital Design And Computer Architecture?

For understanding SystemVerilog, I have been writing the codes on the Digital Design And the Computer Architecture. So, I wrote the first example and the testbench in the book. Design module sillyfunction(input logic a,b,c, …
asimtot
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Getting an error using parameter in Verilog

I’m new to using verilog for verifying memories. I’ve defined address width and data width in the testbench as parameters, and I’m trying like this below which is giving me an error: parameter ADDRESS_WIDTH =9 And down below in the testbench…
Verilog- enthusiastic
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My testbench always shows X as the outputs

I'm not able to identify the bug, but all the code seems logically and syntactically right. The value of sum and carry in the testbench are always X. There are two modules, one for an 8bit adder and another for a 16bit adder : module adder_8(in1 ,…
AmazingMonk
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Passing a varying number of macro arguments as a string in System Verilog

I have an existing code that uses some macro definitions in order to display messages from my test cases. I want to change the implementation of these macros, however, as these macros are extensively used in already existing testcases, I am looking…
wlowo
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Flip flop testbench shows incorrect values

I need to implement the testbench for the 4 flipflops module that are in the design.sv interface. The modules foo1, foo2 and bar2 are working properly (you can see this when you run, the expected values are the same as the output values) except the…
Connor
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How do I use assert in VHDL correctly?

I have in VHDL a code segment which makes me unsure if it's right: a and b are std_logic_vectors. c1 and c0 are std_logic. Is this correct written? Especially the part "c1 = '1' and c0 = '0'" struggels with me. if unsigned(a) > unsigned(b) then …
bilaljo
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VHDL assert testbench with for loop

I've a VHDL problem: for a homework we've to write a testbench with assert for our VHDL designed circuit. We should test every signal combination for a for bit comparator. I thought to solve this with a for loop, like this: architecture ts of…
bilaljo
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EDAplayground error: Execution interrupted or reached maximum runtime

It has some error in my code, but I can't find anything wrong with my code. EDA Playground says: Execution interrupted or reached maximum runtime. Here is my code: forever #5 clk = ~clk;
full_adder0
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What is the advantage of using a testbench rather than a ".do" file in ModelSim?

What is the advantage of using a testbench rather than a ".do" file in ModelSim? A ".do" file allows me to force and examine ports. The testbench seems to do exactly the same thing. So why use a testbench and not a ".do" file? Thank you!
Tal J
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Apply initial time offset to clock signal

If my clock signal toggles every 40ns but I want it to start toggling only after a specific delay, let's say 15ns, how can I do so using a Verilog testbench?
qwertyuiop
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Dynamic casting in SV using $cast function and task

How can we tell if the calling of $cast is of a function or of a task. How would calling of each differ? One thing I understand is that with the function call, I'll be able to use assert(). But other than that, what tells us if the call is of the…
Timothy Grant
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How to send data over AXI Stream using Xiling VIP IP

I'm trying to use AXI Stream Verification IP but I cannot figure out how to use it in slave mode. How can I get the data out of agent: import axi4stream_vip_v1_0_1_pkg::*; import axis_vip_master_pkg::*; import axis_vip_slave_pkg::*; module…
Maciej Piechotka
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Race condition between signals

I've encountered a test bench which can essentially be boiled down to the below example: clock and signals are changed in the in the same timestep with blocking assignments. I believe this causes a race condition between the clock and the two ctrlX…
user11610
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