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This is simple VHDL design for flipflop. Please show me how to import vhdl file to systemverilog so i can do verification using UVM. If there is better way then wrapper please tell me. I am using Questa 10.4d.

library ieee;
use ieee. std_logic_1164.all;
use ieee. std_logic_arith.all;
use ieee. std_logic_unsigned.all;

entity flipflop is
    port(D, Clock : in  std_logic;
         Q : out  std_logic);
end flipflop;

architecture behavioral of flipflop is
begin
  process(CLOCK)
  begin
    if(CLOCK='1' and CLOCK'EVENT) then
      Q<=D;
    end if;
  end process;
end behavioral;
Morten Zilmer
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Sanjin Arsenovic
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    Depending what you mean by a "better way" you might consider keeping it pure VHDL and using the OSVVM library www.osvvm.org for advanced verification techniques. Works with several simulators including open-source ghdl ("ghdl-updates" at sourceforge) –  Apr 20 '16 at 13:29

1 Answers1

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Questa lets you import VHDL entities without creating a wrapper. Check the user manual for mixed language simulation and look at the examples in questadir/examples/mixedlang/sv_vhdl_param

dave_59
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